SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
For this combination the Tx Buffers section in the Message RAM is separated in two parts:
If MCAN_TXBC[29-24] TFQS field is empty (zero) - only Dedicated Tx Buffers are used.
Tx prioritization:
Figure 12-2744 shows Mixed Dedicated Tx Buffers/Tx Queue example.