SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-84 shows the mapping of events to the MCU_ESM0. Note that pulse event inputs are triple redundent so that there are three separate inputs for each pulse event (all to the same source signal) but only one connection is shown here.
Interrupt Input Line | Interrupt ID | Interrupt Name |
---|---|---|
MCU_ESM0_LVL_IN_0 | 0 | MCU_PLLFRAC2_SSMOD0_LOCKLOSS_IPCFG_0 |
MCU_ESM0_LVL_IN_1 | 1 | MCU_PLLFRAC2_SSMOD1_LOCKLOSS_IPCFG_0 |
MCU_ESM0_LVL_IN_2 | 2 | MCU_PLLFRAC2_SSMOD2_LOCKLOSS_IPCFG_0 |
MCU_ESM0_LVL_IN_10 | 10 | MCU_ADC0_ECC_CORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_11 | 11 | MCU_ADC0_ECC_UNCORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_12 | 12 | MCU_ADC1_ECC_CORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_13 | 13 | MCU_ADC1_ECC_UNCORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_14 | 14 | MCU_CPSW0_ECC_SEC_PEND_0 |
MCU_ESM0_LVL_IN_15 | 15 | MCU_CPSW0_ECC_DED_PEND_0 |
MCU_ESM0_LVL_IN_16 | 16 | MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0 |
MCU_ESM0_LVL_IN_17 | 17 | MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0 |
MCU_ESM0_LVL_IN_18 | 18 | MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0 |
MCU_ESM0_LVL_IN_19 | 19 | MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0 |
MCU_ESM0_LVL_IN_20 | 20 | MCU_I3C0_PCLK_ECC_UNCORR_LVL_0 |
MCU_ESM0_LVL_IN_21 | 21 | MCU_I3C0_SCLK_ECC_UNCORR_LVL_0 |
MCU_ESM0_LVL_IN_22 | 22 | MCU_I3C1_PCLK_ECC_UNCORR_LVL_0 |
MCU_ESM0_LVL_IN_23 | 23 | MCU_I3C1_SCLK_ECC_UNCORR_LVL_0 |
MCU_ESM0_LVL_IN_24 | 24 | MCU_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0 |
MCU_ESM0_LVL_IN_25 | 25 | MCU_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0 |
MCU_ESM0_LVL_IN_26 | 26 | MCU_FSS0_OSPI_1_OSPI_ECC_CORR_LVL_INTR_0 |
MCU_ESM0_LVL_IN_27 | 27 | MCU_FSS0_OSPI_1_OSPI_ECC_UNCORR_LVL_INTR_0 |
MCU_ESM0_LVL_IN_28 | 28 | MCU_FSS0_HYPERBUS1P0_0_HPB_ECC_CORR_LEVEL_0 |
MCU_ESM0_LVL_IN_29 | 29 | MCU_FSS0_HYPERBUS1P0_0_HPB_ECC_UNCORR_LEVEL_0 |
MCU_ESM0_LVL_IN_30 | 30 | MCU_FSS0_MISC_0_ECC_INTR_ERR_PEND_0 |
MCU_ESM0_LVL_IN_31 | 31 | MCU_FSS0_FSAS_0_ECC_INTR_ERR_PEND_0 |
MCU_ESM0_LVL_IN_32 | 32 | MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 |
MCU_ESM0_LVL_IN_33 | 33 | MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 |
MCU_ESM0_LVL_IN_34 | 34 | MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0 |
MCU_ESM0_LVL_IN_35 | 35 | MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0 |
MCU_ESM0_LVL_IN_36 | 36 | MCU_R5FSS0_CORE0_EXP_INTR_0 |
MCU_ESM0_LVL_IN_37 | 37 | MCU_R5FSS0_CORE1_EXP_INTR_0 |
MCU_ESM0_LVL_IN_39 | 39 | MCU_MASTER_SAFETY_GASKET0_TIMED_OUT_0 |
MCU_ESM0_LVL_IN_40 | 40 | MCU_NAVSS0_MODSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_41 | 41 | MCU_NAVSS0_MODSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_42 | 42 | MCU_NAVSS0_UDMASS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_43 | 43 | MCU_NAVSS0_UDMASS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_44 | 44 | MASTER_SAFETY_GASKET16_TIMED_OUT_0 |
MCU_ESM0_LVL_IN_45 | 45 | MASTER_SAFETY_GASKET17_TIMED_OUT_0 |
MCU_ESM0_LVL_IN_46 | 46 | MASTER_SAFETY_GASKET18_TIMED_OUT_0 |
MCU_ESM0_LVL_IN_47 | 47 | MASTER_SAFETY_GASKET19_TIMED_OUT_0 |
MCU_ESM0_LVL_IN_48 | 48 | MCU_TIMEOUT_64B3_TRANS_ERR_LVL_0 |
MCU_ESM0_LVL_IN_49 | 49 | MCU_TIMEOUT_64B4_TRANS_ERR_LVL_0 |
MCU_ESM0_LVL_IN_50 | 50 | MCU_R5FSS0_COMMON0_ECC_SE_TO_ESM_0_0 |
MCU_ESM0_LVL_IN_51 | 51 | MCU_R5FSS0_COMMON0_ECC_DE_TO_ESM_0_0 |
MCU_ESM0_LVL_IN_52 | 52 | MCU_R5FSS0_COMMON0_ECC_SE_TO_ESM_1_0 |
MCU_ESM0_LVL_IN_53 | 53 | MCU_R5FSS0_COMMON0_ECC_DE_TO_ESM_1_0 |
MCU_ESM0_LVL_IN_54 | 54 | MCU_TIMER0_INTR_PEND_0 |
MCU_ESM0_LVL_IN_55 | 55 | MCU_TIMER1_INTR_PEND_0 |
MCU_ESM0_LVL_IN_56 | 56 | MCU_TIMER2_INTR_PEND_0 |
MCU_ESM0_LVL_IN_57 | 57 | MCU_TIMER3_INTR_PEND_0 |
MCU_ESM0_LVL_IN_58 | 58 | MCU_TIMER4_INTR_PEND_0 |
MCU_ESM0_LVL_IN_59 | 59 | MCU_TIMER5_INTR_PEND_0 |
MCU_ESM0_LVL_IN_60 | 60 | MCU_TIMER6_INTR_PEND_0 |
MCU_ESM0_LVL_IN_61 | 61 | MCU_TIMER7_INTR_PEND_0 |
MCU_ESM0_LVL_IN_62 | 62 | MCU_TIMER8_INTR_PEND_0 |
MCU_ESM0_LVL_IN_63 | 63 | MCU_TIMER9_INTR_PEND_0 |
MCU_ESM0_LVL_IN_64 | 64 | MCU_MSRAM_1MB0_ECC_CORR_LEVEL_0 |
MCU_ESM0_LVL_IN_65 | 65 | MCU_MSRAM_1MB0_ECC_UNCORR_LEVEL_0 |
MCU_ESM0_LVL_IN_66 | 66 | MCU_SA2_UL0_SA_UL_ECC_CORR_LEVEL_0 |
MCU_ESM0_LVL_IN_67 | 67 | MCU_SA2_UL0_SA_UL_ECC_UNCORR_LEVEL_0 |
MCU_ESM0_LVL_IN_70 | 70 | MCU_ECC_AGGR0_CORR_LEVEL_0 |
MCU_ESM0_LVL_IN_71 | 71 | MCU_ECC_AGGR0_UNCORR_LEVEL_0 |
MCU_ESM0_LVL_IN_73 | 73 | MCU_PBIST1_DFT_PBIST_SAFETY_ERROR_0 |
MCU_ESM0_LVL_IN_74 | 74 | MCU_PBIST0_DFT_PBIST_SAFETY_ERROR_0 |
MCU_ESM0_LVL_IN_75 | 75 | MCU_PBIST2_DFT_PBIST_SAFETY_ERROR_0 |
MCU_ESM0_LVL_IN_76 | 76 | MCU_TIMEOUT_64B2_TRANS_ERR_LVL_0 |
MCU_ESM0_LVL_IN_77 | 77 | MCU_TIMEOUT_INFRA0_SAFEG_TRANS_ERR_LVL_0 |
MCU_ESM0_LVL_IN_78 | 78 | MCU_TIMEOUT_FW1_SAFEG_TRANS_ERR_LVL_0 |
MCU_ESM0_LVL_IN_80 | 80 | MCU_I3C0_I3C_NONFATAL__INT_0 |
MCU_ESM0_LVL_IN_81 | 81 | MCU_I3C0_I3C_FATAL__INT_0 |
MCU_ESM0_LVL_IN_82 | 82 | MCU_I3C1_I3C_NONFATAL__INT_0 |
MCU_ESM0_LVL_IN_83 | 83 | MCU_I3C1_I3C_FATAL__INT_0 |
MCU_ESM0_LVL_IN_86 | 86 | MCU_DCC0_INTR_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_87 | 87 | MCU_DCC1_INTR_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_88 | 88 | MCU_DCC2_INTR_ERR_LEVEL_0 |
MCU_ESM0_LVL_IN_95 | 95 | GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0 |
MCU_ESM0_PLS_IN_96 | 96 | MCU_R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0 |
MCU_ESM0_PLS_IN_97 | 97 | MCU_R5FSS0_COMMON0_COMPARE_ERR_PULSE_0 |
MCU_ESM0_PLS_IN_98 | 98 | MCU_R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0 |
MCU_ESM0_PLS_IN_99 | 99 | MCU_R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0 |
MCU_ESM0_PLS_IN_100 | 100 | MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0 |
MCU_ESM0_PLS_IN_104 | 104 | MCU_RTI0_INTR_WWD_0 |
MCU_ESM0_PLS_IN_105 | 105 | MCU_RTI1_INTR_WWD_0 |