SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The UART function contains a programmable baud generator and a set of fixed dividers that divide the 48-MHz clock input down to the expected baud rate.
Figure 12-418 shows the baud rate generator and associated controls.
Before initializing or modifying clock parameter controls (UART_DLH, UART_DLL), UART_MDR1[2-0] MODE_SELECT = DISABLE must be set to 0x7. Failure to observe this rule can result in unpredictable module behavior.