SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The read enable (REN) input to the RAMs instantiated in this module are constantly tied to 1’b1. As a result, read is continuously in progress.
In order to test ECC single error injection on a particular RAM row, the following conditions have to be maintained before setting the ADC_ECC_CTRL[3] FORCE_SEC bit: