SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes SerDes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 12-1953 shows the integration of the SerDes modules in the device.
Table 12-3870 through Table 12-3872 summarize the integration of SerDes in device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
SERDES0 | PSC0 | PD5 | LPSC64 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
SERDES0 | SERDES0_ICLK | MAIN_SYSCLK0/4 | PLL_CTRL0 | VBUS interface clock |
CMN_REFCLK_INT | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | Internal reference clock from device sources. Software selectable. See Section 12.2.5.3.1.3 | |
HFOSC1_CLKOUT | HFOSC1 | |||
MAIN_PLL3_HSDIV4_CLKOUT | PLL3 | |||
MAIN_PLL2_HSDIV4_CLKOUT | PLL2 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
SERDES0 | SERDES0_RST | MOD_G_RST | LPSC64 | Serdes LPSC reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
SERDES0 | PHY_PWR_TIMEOUT_LVL_0 | ESM0_LVL_IN_308 | ESM0 | Lane power timeout interrupt | Level |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
SERDES0 | - | - | - | No PDMA channels to external DMA engines | - |