The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster (COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute cluster.
Table 8-1 shows MSMC modules allocation within device domains.
Table 8-1 MSMC Modules Allocation within Device DomainsModule Instance | Domain |
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WKUP | MCU | MAIN |
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MSMC | - | - | ✓ |
Figure 8-1 shows an overview of the MSMC and its surrounding modules.
MSMC supports the following features:
- 1MB (2 banks x 512kB) SRAM with ECC:
- Shared coherent level 2/level 3 memory-mapped SRAM
- Shared coherent level 3 cache
- 256-bit processor port bus and 40-bit physical address bus
- Coherent unified bi-directional interfaces to connect to processors or device masters
- One infrastructure master interface
- Single external memory master interface
- Supports distributed virtual system
- Bandwidth management with starvation bound
- Two-level QoS support for real-time/nonreal-time split
- Security firewall flush support for SRAM/cache and external memory
- Functional reliability:
- SEC/DED protection on all data and tag memories with hardware scrubbing
- SEC/DED protection on all data pipelines
- Data memory address hamming protection
- Coherent interconnect transaction metadata parity protection
- Trace and debugging support
- Supports dynamic clock gating on all logic units
- MSMC is always on when VD_CORE is on