SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
During DeepSleep power saving mode, the GPIO functional clock is powered down. This would the WKUP_GPIOu (u = 0, 1) modules from detecting transitions on GPIO pins to be used as wakeup from DeepSleep events. In order to correct this issue, special clocking and controls are implemented as part of the WKUP_GPIOu (u = 0, 1) integration to allow GPIO transition to remain detectable.
A clock MUX is provided to allow the GPIO clock to be switched to an on-chip clock source prior to gating of the standard clock source (MCU_SYSCLK0/6) and power-down of the off-chip WKUP_HFOSC0 oscillator. This clock MUX is controlled by the WKUP_CTRL_MMR0 register bits.
Because there is no asynchronous bridge between the WKUP_GPIOu (u = 0, 1) modules and the WKUP_CBASS0, the module register may only be accessed when it is clocked using the synchronous MCU_SYSCLK0/6 clock source. Prior to switching the clock source to prepare for DeepSleep, all clock accesses to the WKUP_GPIOu (u = 0, 1) modules must be blocked through the dedicated LPSC5 using a clock stop request. Note that when wakeup functionality for the WKUP_GPIOu (u = 0, 1) is enabled, (through a WKUP_CTRL_MMR0 registers), this clock stop request is not actually propagate to the WKUP_GPIOu (u = 0, 1) module (or stop it is clock). Instead, it will be fed back to the LPSC3 as a clock stop acknowledged. This will cause the associated WKUP_CBASS0 to route all future WKUP_GPIO register accesses to a null endpoint. The WKUP_GPIOu (u = 0, 1) LPSC3 must be maintained in clock stop mode until MCU_SYSCLK0/6 is fully restored upon wakeup from DeepSleep and the WKUP_GPIOu (u = 0, 1) clock MUX has finished switching back the normal clock source.
The following are the steps required (expected to be performed by the DMSC) to enable WKUP_GPIOu (u = 0, 1) wakeup events prior to DeepSleep:
Once in DeepSleep mode, any GPIO transition (low to high or high to low) intended to cause a wakeup must be maintained at its new value for at least 0x2 of the selected functional clock (CLK_32K_RC or CLK_12M_RC) maximum periods to ensure proper detection. (Note that process variance of the RC clocks must be taken into account). The detected event will be latched in the GPIO_INTSTAT register and the WKUP_GPIOMUX_INTRTR0 wakeup event sent to the DMSC to trigger the wakeup FSM.
After wakeup, the DMSC must restore the MCU_SYSCLK0/6 operation to allow the wakeup source event to be latched within the DMSC. Once this is done the DMSC may restore access to the WKUP_GPIOu (u = 0, 1) module by reversing the steps above:
The specific GPIO source of the wakeup event may now be determined by reading the GPIO_INTSTAT register and cleared by writing 0x1 to the set bits of the same register.