SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Each EPWM module has an EPWMTBCLKEN module input used to individually enable / disable its EPWM time-base clock. The EPWM time-base clock enable input comes from the EPWMn_CTRL (where n = 0 to 5) register in CTRL_MMR0 module, as follows:
This individual TBCLKEN control can be used to align the EPWM time base clock. TB_CLKEN bit set to 0h, holds the TBCLK generation counter in its reset state. When TB_CLKEN is set to 1h, then the TBCLK generation counter is allowed to count.