SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 12-131 through Figure 12-137 are procedure flow charts for programming the F/S and HS I2C modes.
The FIFO clearing can be made when the module is configured as transmitter, the receiver send a NACK in the middle of the transfer, and there is still data in the FIFO.
In HS mode, the Sr condition and clock frequency switching are automatically generated by the multicontroller I2C.
The FIFO clearing can be made when the module is configured as transmitter, the receiver send a NACK in the middle of the transfer, and there is still data in the FIFO.
In HS mode, the Sr condition and clock frequency switching are automatically generated by the multicontroller I2C.