SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There is an isolation mechanism between the WKUP, MCU, and MAIN domain, and also between some components inside the MAIN domain. This is accomplished by initiator timeout gasket (MTOGs) and target timeout gaskets (STOGs). MTOGs are inserted on certain initiators while STOGs are inserted either directly on certain targets, or on the CBASS (interconnect) port enabling connection to a group of such targets.
When a fault happens on the initiator interface side, the MTOG provides capability to flush out all pending transactions while preventing the faulty initiator interface from issuing more transactions. It also has logic to track the idle state when all pending transactions are completed. The initiator cannot be brought down or reset unless the MTOG enters idle state. There are registers in the CTRL_MMR0 associated with the MTOG modules.
When a fault happens on the target interface side, the STOG provides capability to terminate the transactions and returns error status back to the initiator, so the interconnect does not stall due to the fault at the target side. There are no CTRL_MMR0 registers for the STOG modules.
All MTOGs and STOGs assert an interrupt when there is a timeout event. See Table 3-3, Table 3-6, and Table 3-9 for the interrupt mapping. Table 3-46 and Table 3-47 show the TOG modules. There are also timeout gaskets in NAVSS0 and COMPUTE_CLUSTER0 but they are not described in this section.
MTOG Module | Location | CTRL_MMR0 Register |
---|---|---|
MTOG0 | GIC0_RD | CTRLMMR_MAIN_MTOG0_CTRL |
MTOG1 | GIC0_WR | CTRLMMR_MAIN_MTOG1_CTRL |
MTOG2 | MMCSD0_RD | CTRLMMR_MAIN_MTOG2_CTRL |
MTOG3 | MMCSD0_WR | CTRLMMR_MAIN_MTOG3_CTRL |
MTOG4 | MMCSD1_RD | CTRLMMR_MAIN_MTOG4_CTRL |
MTOG5 | MMCSD1_WR | CTRLMMR_MAIN_MTOG5_CTRL |
MTOG10 | PCIE1_RD | CTRLMMR_MAIN_MTOG10_CTRL |
MTOG11 | PCIE1_WR | CTRLMMR_MAIN_MTOG11_CTRL |
MTOG12 | USB3SS0_RD | CTRLMMR_MAIN_MTOG12_CTRL |
MTOG13 | USB3SS0_WR | CTRLMMR_MAIN_MTOG13_CTRL |
MTOG16 | R5FSS0_CORE0_MEM_RD | CTRLMMR_MAIN_MTOG16_CTRL |
MTOG17 | R5FSS0_CORE0_MEM_WR | CTRLMMR_MAIN_MTOG17_CTRL |
MTOG18 | R5FSS0_CORE1_MEM_RD | CTRLMMR_MAIN_MTOG18_CTRL |
MTOG19 | R5FSS0_CORE1_MEM_WR | CTRLMMR_MAIN_MTOG19_CTRL |
MCU_MTOG0 | CBASS0 to MCU_CBASS0 | CTRLMMR_MCU_MTOG0_CTRL |
STOG Module | Location |
---|---|
WKUP_TIMEOUT_INFRA0 | WKUP_CBASS0 to INFRA_CBASS0 |
MCU_TIMEOUT_64B3 | MCU_CBASS0 to MCU_FSS0 |
MCU_TIMEOUT_64B2 | MCU_CBASS0 to CBASS_RC0 |
MCU_TIMEOUT_INFRA0 | MCU_CBASS0 to INFRA_CBASS0 |
TIMEOUT0 | INFRA_CBASS0 to INFRA_NS_CBASS0 |
TIMEOUT1 | CBASS_IPPHY_S0 to CBASS_IPPHY0 |
TIMEOUT2 | CBASS_RC0 to CBASS_RC_CFG0 |
TIMEOUT3 | CBASS_RC0 to GPMC0 |
TIMEOUT4 | CBASS_RC0 to CBASS_HC2_0 |