SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3850 lists the memory-mapped registers for the USB_RAMS_INJ_CFG registers. All register offset addresses not listed in Table 12-3850 should be considered as reserved locations and the register contents should not be modified.
Error Injector Registers
Instance | Base Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0000h |
Offset | Acronym | Register Name | USB0_RAMS_INJ_CFG Physical Address |
---|---|---|---|
0h | USB_PID | Revision Register | 02A1 0000h |
4h | USB_INFO | Info Register | 02A1 0004h |
8h | USB_SFT_RST | Global Soft Reset Register | 02A1 0008h |
10h | USB_BIT1 | Bit 1 Mask Register | 02A1 0010h |
14h | USB_BIT2 | Bit 2 Mask Register | 02A1 0014h |
18h | USB_TRGT | Target Select | 02A1 0018h |
1Ch | USB_CTRL | Control Register | 02A1 001Ch |
20h | USB_STATUS | Control Register | 02A1 0020h |
USB_PID is shown in Figure 12-1943 and described in Table 12-3852.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-0h | R-0h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Register scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNC | R | 0h | Module ID |
15-11 | RTL | R | 0h | RTL revision. |
10-8 | MAJOR | R | 0h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 1h | Minor revision |
USB_INFO is shown in Figure 12-1944 and described in Table 12-3854.
Return to Summary Table.
The Info Register gives the configuration Inforrmation of this module.
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENDPOINTS | ||||||||||||||
R-X | R-1Eh | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5-0 | ENDPOINTS | R | 1Eh | Total number of Targets supported by this configuration |
USB_SFT_RST is shown in Figure 12-1945 and described in Table 12-3856.
Return to Summary Table.
The Global Soft Reset Register clears all programmable registers and returns the injector to idle state
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | KEY | ||||||||||||||||||||||||||||||
W-X | W-0h | ||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | X | |
3-0 | KEY | W | 0h | Write 4'b1010 to issue a soft reset. |
USB_BIT1 is shown in Figure 12-1946 and described in Table 12-3858.
Return to Summary Table.
This register defines the first bit to be flipped when injection is enabled
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BIT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | BIT1 | R/W | 0h | First bit to be flipped on an error injection |
USB_BIT2 is shown in Figure 12-1947 and described in Table 12-3860.
Return to Summary Table.
This register defines the second bit to be flipped if 2-bit injection is enabled
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BIT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | BIT2 | R/W | 0h | Second bit to be flipped on an error injection if 2-bit injection is chosen. |
USB_TRGT is shown in Figure 12-1948 and described in Table 12-3862.
Return to Summary Table.
This is the target selection register
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRGT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4-0 | TRGT | R/W | 0h | Select which target to interact with. |
USB_CTRL is shown in Figure 12-1949 and described in Table 12-3864.
Return to Summary Table.
Controls the injection
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TRGT | ||||||
R/W-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | TWOBIT | ONEBIT | ||||
R/W-X | R-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | X | |
12-8 | TRGT | R | 0h | Indicates which target is selected by the USB_TRGT register |
7-3 | RESERVED | R/W | X | |
2 | DONE | R | 0h | Indicates that the target selected by USB_TRGT has
completed error injection. |
1 | TWOBIT | R/W | 0h | Write 1 to trigger a 2-bit error in target
selected by USB_TRGT register. |
0 | ONEBIT | R/W | 0h | Write 1 to trigger a 1-bit error in target
selected by USB_TRGT register. |
USB_STATUS is shown in Figure 12-1950 and described in Table 12-3866.
Return to Summary Table.
Controls the injection
Instance | Physical Address |
---|---|
USB0_RAMS_INJ_CFG | 02A1 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ARMED | RESERVED | |||||
R-X | R-0h | R-X | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | X | |
2 | ARMED | R | 0h | Indicates that the target selected by USB_TRGT is ARMED for error injection |
1-0 | RESERVED | R | X |