SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3758 lists the memory-mapped registers for the PCIE_ECC_AGGR1. All register offset addresses not listed in Table 12-3758 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3000h |
Offset | Acronym | Register Name | PCIE1_CORE_ECC_AGGR1 Physical Address |
---|---|---|---|
0h | PCIE_ECC1_REV | Aggregator Revision Register | 02A0 3000h |
8h | PCIE_ECC1_VECTOR | ECC Vector Register | 02A0 3008h |
Ch | PCIE_ECC1_STAT | Misc Status | 02A0 300Ch |
10h + formula | PCIE_ECC1_RESERVED_SVBUS_y | Reserved Area for Serial VBUS Registers | 02A0 3010h + formula |
3Ch | PCIE_ECC1_SEC_EOI_REG | EOI Register | 02A0 303Ch |
40h | PCIE_ECC1_SEC_STATUS_REG0 | Interrupt Status Register 0 | 02A0 3040h |
80h | PCIE_ECC1_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A0 3080h |
C0h | PCIE_ECC1_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A0 30C0h |
13Ch | PCIE_ECC1_DED_EOI_REG | EOI Register | 02A0 313Ch |
140h | PCIE_ECC1_DED_STATUS_REG0 | Interrupt Status Register 0 | 02A0 3140h |
180h | PCIE_ECC1_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A0 3180h |
1C0h | PCIE_ECC1_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A0 31C0h |
200h | PCIE_ECC1_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 02A0 3200h |
204h | PCIE_ECC1_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 02A0 3204h |
208h | PCIE_ECC1_AGGR_STATUS_SET | AGGR interrupt status set Register | 02A0 3208h |
20Ch | PCIE_ECC1_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 02A0 320Ch |
PCIE_ECC1_REV is shown in Figure 12-1901 and described in Table 12-3760.
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Revision parameters
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-5h | R-2h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 5h | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 1h | Minor version |
PCIE_ECC1_VECTOR is shown in Figure 12-1902 and described in Table 12-3762.
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Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
PCIE_ECC1_STAT is shown in Figure 12-1903 and described in Table 12-3764.
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Misc Status
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 300Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 4h | Indicates the number of RAMS serviced by the ECC aggregator |
PCIE_ECC1_RESERVED_SVBUS_y is shown in Figure 12-1904 and described in Table 12-3766.
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Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
PCIE_ECC1_SEC_EOI_REG is shown in Figure 12-1905 and described in Table 12-3768.
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EOI Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 303Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
PCIE_ECC1_SEC_STATUS_REG0 is shown in Figure 12-1906 and described in Table 12-3770.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_PEND | RPLYBUF_RAMECC_PEND | RXCPLFIFO_RAMECC_PEND | PNPFIFO_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for pnpfifo_ramecc_pend |
PCIE_ECC1_SEC_ENABLE_SET_REG0 is shown in Figure 12-1907 and described in Table 12-3772.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_ENABLE_SET | RPLYBUF_RAMECC_ENABLE_SET | RXCPLFIFO_RAMECC_ENABLE_SET | PNPFIFO_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pnpfifo_ramecc_pend |
PCIE_ECC1_SEC_ENABLE_CLR_REG0 is shown in Figure 12-1908 and described in Table 12-3774.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 30C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_ENABLE_CLR | RPLYBUF_RAMECC_ENABLE_CLR | RXCPLFIFO_RAMECC_ENABLE_CLR | PNPFIFO_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pnpfifo_ramecc_pend |
PCIE_ECC1_DED_EOI_REG is shown in Figure 12-1909 and described in Table 12-3776.
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EOI Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 313Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
PCIE_ECC1_DED_STATUS_REG0 is shown in Figure 12-1910 and described in Table 12-3778.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_PEND | RPLYBUF_RAMECC_PEND | RXCPLFIFO_RAMECC_PEND | PNPFIFO_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for pnpfifo_ramecc_pend |
PCIE_ECC1_DED_ENABLE_SET_REG0 is shown in Figure 12-1911 and described in Table 12-3780.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_ENABLE_SET | RPLYBUF_RAMECC_ENABLE_SET | RXCPLFIFO_RAMECC_ENABLE_SET | PNPFIFO_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pnpfifo_ramecc_pend |
PCIE_ECC1_DED_ENABLE_CLR_REG0 is shown in Figure 12-1912 and described in Table 12-3782.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 31C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXISRODR_RAMECC_ENABLE_CLR | RPLYBUF_RAMECC_ENABLE_CLR | RXCPLFIFO_RAMECC_ENABLE_CLR | PNPFIFO_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | AXISRODR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axisrodr_ramecc_pend |
2 | RPLYBUF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for rplybuf_ramecc_pend |
1 | RXCPLFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for rxcplfifo_ramecc_pend |
0 | PNPFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pnpfifo_ramecc_pend |
PCIE_ECC1_AGGR_ENABLE_SET is shown in Figure 12-1913 and described in Table 12-3784.
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AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
PCIE_ECC1_AGGR_ENABLE_CLR is shown in Figure 12-1914 and described in Table 12-3786.
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AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
PCIE_ECC1_AGGR_STATUS_SET is shown in Figure 12-1915 and described in Table 12-3788.
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AGGR interrupt status set Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 3208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
PCIE_ECC1_AGGR_STATUS_CLR is shown in Figure 12-1916 and described in Table 12-3790.
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AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR1 | 02A0 320Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |