SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The emulation control input and register bits (SOFT and FREE in the UDMA_EMU_CTRL register) allow DMA operation to be suspended. When the emulation suspend state is entered, the DMA will stop processing receive and transmit packets for each channel at the next packet boundary. Any packet currently in reception or transmission will be completed normally without suspension. Emulation control is implemented for compatibility with other peripherals. Table 10-217 shows the operations of the emulation control input and register bits.
Emulation Control Input | SOFT | FREE | Description |
---|---|---|---|
0 | X | X | Normal Operation |
1 | 0 | 0 | Normal Operation |
1 | 1 | 0 | Emulation Suspend |
1 | X | 1 | Normal Operation |