SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 11-128 lists the memory-mapped registers for the CMPEVT_INTRTR0. All register offset addresses not listed in Table 11-128 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CMPEVENT_INTRTR0_INTR_ROUTER_CFG | 00A3 0000h |
Offset | Acronym | Register Name | CMPEVENT_INTRTR0_ INTR_ROUTER_CFG Physical Address |
---|---|---|---|
0h | CMPEVT_INTRTR0_PID | Peripheral identification register | 00A3 0000h |
4h + formula | CMPEVT_INTRTR0_MUXCNTL_y | Event mux control register | 00A3 0004h + formula |
CMPEVT_INTRTR0_PID is shown in Figure 11-61 and described in Table 11-130.
Return to Summary Table.
Peripheral identification register. Uniquely identifies the module and its specific revision.
Instance | Physical Address |
---|---|
CMPEVENT_INTRTR0_INTR_ROUTER_CFG | 00A3 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66948100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66948100h | TI internal data. Identifies revision of peripheral. |
CMPEVT_INTRTR0_MUXCNTL_y is shown in Figure 11-62 and described in Table 11-132.
Return to Summary Table.
Event mux control register.
Offset = 4h + (y * 4h); where y = 0h to Fh.
Instance | Physical Address |
---|---|
CMPEVENT_INTRTR0_INTR_ROUTER_CFG | 00A3 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INT_ENABLE | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16 | INT_ENABLE | R/W | 0h | Enable for event output N |
15-4 | RESERVED | R | 0h | Reserved |
3-0 | ENABLE | R/W | 0h | Mux control for event output N |