SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Not all timer inputs and outputs are pinned out of the device. Through the timer I/O muxing registers the inputs and outputs of the MAIN domain timers can be made available on the TIMER_IO[7:0] device pads.
Each timer input can be configured to be driven by one of the TIMER_IO[7:0] pads through the corresponding bits in the CTRLMMR_TIMER0_CTRL to CTRLMMR_TIMER19_CTRL registers. Each of the TIMER_IO[7:0] pads can be configured to be driven by any of the timer outputs through the corresponding bits in the CTRLMMR_TIMERIO0_CTRL to CTRLMMR_TIMERIO7_CTRL registers. Figure 5-334 shows the TIMER I/O multiplexing scheme for the MAIN domain.
For more information about each timer, see Section 12.6.3Timers.