SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-357 lists the memory-mapped registers for the UDMASS_UDMAP0_CFG_TCHANRT. All register offset addresses not listed in Table 10-357 should be considered as reserved locations and the register contents should not be modified.
The UDMA-P Tx Channel Realtime Registers region is accessed by setting the cdma_cfg_rsel signal to 4 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0000h |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT Physical Address | MCU_NAVSS0_UDMASS_UDMAP_TCHANRT Physical Address |
---|---|---|---|---|
0h + formula | UDMA_TRT_CTL_j | Tx Channel Realtime Control Register | 3500 0000h + formula | 2AA0 0000h + formula |
8h + formula | UDMA_TRT_SWTRIG_j | Tx Channel Realtime Software Trigger Register | 3500 0008h + formula | 2AA0 0008h + formula |
80h + formula | UDMA_TRT_STDATA_j_Y | Tx Channel Realtime State Data Register | 3500 0080h + formula | 2AA0 0080h + formula |
200h + formula | UDMA_TRT_PEER0_j | Tx Channel Real-time Remote Peer Register 0 | 3500 0200h + formula | 2AA0 0200h + formula |
204h + formula | UDMA_TRT_PEER1_j | Tx Channel Real-time Remote Peer Register 1 | 3500 0204h + formula | 2AA0 0204h + formula |
208h + formula | UDMA_TRT_PEER2_j | Tx Channel Real-time Remote Peer Register 2 | 3500 0208h + formula | 2AA0 0208h + formula |
20Ch + formula | UDMA_TRT_PEER3_j | Tx Channel Real-time Remote Peer Register 3 | 3500 020Ch + formula | 2AA0 020Ch + formula |
210h + formula | UDMA_TRT_PEER4_j | Tx Channel Real-time Remote Peer Register 4 | 3500 0210h + formula | 2AA0 0210h + formula |
214h + formula | UDMA_TRT_PEER5_j | Tx Channel Real-time Remote Peer Register 5 | 3500 0214h + formula | 2AA0 0214h + formula |
218h + formula | UDMA_TRT_PEER6_j | Tx Channel Real-time Remote Peer Register 6 | 3500 0218h + formula | 2AA0 0218h + formula |
21Ch + formula | UDMA_TRT_PEER7_j | Tx Channel Real-time Remote Peer Register 7 | 3500 021Ch + formula | 2AA0 021Ch + formula |
220h + formula | UDMA_TRT_PEER8_j | Tx Channel Real-time Remote Peer Register 8 | 3500 0220h + formula | 2AA0 0220h + formula |
224h + formula | UDMA_TRT_PEER9_j | Tx Channel Real-time Remote Peer Register 9 | 3500 0224h + formula | 2AA0 0224h + formula |
228h + formula | UDMA_TRT_PEER10_j | Tx Channel Real-time Remote Peer Register 10 | 3500 0228h + formula | 2AA0 0228h + formula |
22Ch + formula | UDMA_TRT_PEER11_j | Tx Channel Real-time Remote Peer Register 11 | 3500 022Ch + formula | 2AA0 022Ch + formula |
230h + formula | UDMA_TRT_PEER12_j | Tx Channel Real-time Remote Peer Register 12 | 3500 0230h + formula | 2AA0 0230h + formula |
234h + formula | UDMA_TRT_PEER13_j | Tx Channel Real-time Remote Peer Register 13 | 3500 0234h + formula | 2AA0 0234h + formula |
238h + formula | UDMA_TRT_PEER14_j | Tx Channel Real-time Remote Peer Register 14 | 3500 0238h + formula | 2AA0 0238h + formula |
23Ch + formula | UDMA_TRT_PEER15_j | Tx Channel Real-time Remote Peer Register 15 | 3500 023Ch + formula | 2AA0 023Ch + formula |
400h + formula | UDMA_TRT_PCNT_j | Tx Channel Real-time Packet Count Statistics Register | 3500 0400h + formula | 2AA0 0400h + formula |
408h + formula | UDMA_TRT_BCNT_j | Tx Channel Real-time Completed Byte Count Statistics Register | 3500 0408h + formula | 2AA0 0408h + formula |
410h + formula | UDMA_TRT_SBCNT_j | Tx Channel Real-time Started Byte Count Statistics Register | 3500 0410h + formula | 2AA0 0410h + formula |
UDMA_TRT_CTL_j is shown in Figure 10-127 and described in Table 10-359.
Return to Summary Table.
The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation.
Offset = 0h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0000h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EN | TDOWN | PAUSE | FTDOWN | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERROR | ||||||
R/W-X | R-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EN | R/W | 0h | This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the attached application block and data loss. When a channel is disabled, the implementation may choose to reset all state for the channel. The pause bit should be asserted instead of clearing enable directly if the intent is to temporarily pause the channel. This field is encoded as follows: 0 = channel is disabled 1 = channel is enabled This field will be cleared by HW after a teardown is requested to indicate that the channel teardown is complete. |
30 | TDOWN | R/W | 0h | Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete. |
29 | PAUSE | R/W | 0h | Channel pause: Setting this bit will cause the channel to pause processing immediately. |
28 | FTDOWN | R/W | 0h | Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set, the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal tx_teardown and is intended to flush the channel to recover any descriptor or TR references which are currently being held by the UDMA-P even if the trigger source is no longer functioning. Uso fo this bit is considered a 'catastrophic' condition and it is assumed that SW will need to perform some re-initialization in the system to re-align events, data buffers, etc. This bit should be set in addition to the tx_teardown bit in order to cause a forced teardown. This field will remain set after a channel teardown is complete. |
27-1 | RESERVED | R/W | X | |
0 | ERROR | R | 0h | Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled. |
UDMA_TRT_SWTRIG_j is shown in Figure 10-128 and described in Table 10-361.
Return to Summary Table.
The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register has no function when the channel is configured for packet mode transfers. A write to this register will cause an event to be sent to this channel.
Offset = 8h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0008h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIGGER | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TRIGGER | W | 0h | Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel |
UDMA_TRT_STDATA_j_Y is shown in Figure 10-129 and described in Table 10-363.
Return to Summary Table.
The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel. These registers should not be accessed without reason while the UDMA-P is operating as accesses will cause performance to decrease as these MMRs are just providing a window into the actual state RAM
Offset = 80h + (j * 1000h) + (y * 4h); where
j = 0h to 3Bh, y = 0h to 1Fh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh, y = 0h to 1Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0080h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATE_INFO | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STATE_INFO | R | 0h | See Tx state mapping table |
UDMA_TRT_PEER0_j is shown in Figure 10-130 and described in Table 10-365.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x400.
Offset = 200h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0200h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0200h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER1_j is shown in Figure 10-131 and described in Table 10-367.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x401.
Offset = 204h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0204h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0204h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER2_j is shown in Figure 10-132 and described in Table 10-369.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x402.
Offset = 208h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0208h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0208h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER3_j is shown in Figure 10-133 and described in Table 10-371.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x403.
Offset = 20Ch + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 020Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 020Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER4_j is shown in Figure 10-134 and described in Table 10-373.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x404.
Offset = 210h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0210h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0210h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER5_j is shown in Figure 10-135 and described in Table 10-375.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x405.
Offset = 214h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0214h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0214h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER6_j is shown in Figure 10-136 and described in Table 10-377.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x406.
Offset = 218h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0218h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0218h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER7_j is shown in Figure 10-137 and described in Table 10-379.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x407.
Offset = 21Ch + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 021Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 021Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER8_j is shown in Figure 10-138 and described in Table 10-381.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x408.
Offset = 220h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0220h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0220h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER9_j is shown in Figure 10-139 and described in Table 10-383.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x409.
Offset = 224h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0224h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0224h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER10_j is shown in Figure 10-140 and described in Table 10-385.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40A.
Offset = 228h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0228h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0228h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER11_j is shown in Figure 10-141 and described in Table 10-387.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40B.
Offset = 22Ch + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 022Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 022Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER12_j is shown in Figure 10-142 and described in Table 10-389.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40C.
Offset = 230h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0230h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0230h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER13_j is shown in Figure 10-143 and described in Table 10-391.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40D.
Offset = 234h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0234h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0234h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER14_j is shown in Figure 10-144 and described in Table 10-393.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40E.
Offset = 238h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0238h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0238h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PEER15_j is shown in Figure 10-145 and described in Table 10-395.
Return to Summary Table.
This register provides access to the remote peer's realtime register at 0x40F.
Offset = 23Ch + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 023Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 023Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PEER_DATA | R/W | 0h | Peer realtime register data (varies by paired peer). |
UDMA_TRT_PCNT_j is shown in Figure 10-146 and described in Table 10-397.
Return to Summary Table.
The statistics registers are supplied to give software applications operational progress status for the channel.
Offset = 400h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0400h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0400h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PCNT | R/W | 0h | Current completed packet count for the channel. |
UDMA_TRT_BCNT_j is shown in Figure 10-147 and described in Table 10-399.
Return to Summary Table.
The statistics registers are supplied to give software applications operational progress status for the channel.
Offset = 408h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0408h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0408h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCNT | R/W | 0h | Current completed payload byte count for the channel. |
UDMA_TRT_SBCNT_j is shown in Figure 10-148 and described in Table 10-401.
Return to Summary Table.
The statistics registers are supplied to give software applications operational progress status for the channel.
Offset = 410h + (j * 1000h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT | 3500 0410h + formula |
MCU_NAVSS0_UDMASS_UDMAP_TCHANRT | 2AA0 0410h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SBCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SBCNT | R/W | 0h | Current started byte count for the channel. |