SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_STAT0 (Port 0). All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4600 0000h |
Offset | Acronym | Register Name | MCU_CPSW0_NUSS_STAT0 Physical Address |
---|---|---|---|
0003A000h | CPSW_STAT0_RXGOODFRAMES | Ethernet Port N Total Number of Good Frames Received | 4603 A000h |
0003A004h | CPSW_STAT0_RXBROADCASTFRAMES | Ethernet Port N Total Number of Good Broadcast Frames Received | 4603 A004h |
0003A008h | CPSW_STAT0_RXMULTICASTFRAMES | Ethernet Port N Total Number of Good Multicast Frames Received | 4603 A008h |
0003A010h | CPSW_STAT0_RXCRCERRORS | Ethernet Port N Total Number of CRC Errors Frames Received | 4603 A010h |
0003A018h | CPSW_STAT0_RXOVERSIZEDFRAMES | Ethernet Port N Total Number of Oversized Frames Received | 4603 A018h |
0003A020h | CPSW_STAT0_RXUNDERSIZEDFRAMES | Ethernet Port N Total Number of Undersized Frames Received | 4603 A020h |
0003A024h | CPSW_STAT0_RXFRAGMENTS | Ethernet Port N Fragments Received Register | 4603 A024h |
0003A028h | CPSW_STAT0_ALE_DROP | Ethernet Port N ALE Drop Register | 4603 A028h |
0003A02Ch | CPSW_STAT0_ALE_OVERRUN_DROP | Ethernet Port N ALE Overrun Drop Register | 4603 A02Ch |
0003A030h | CPSW_STAT0_RXOCTETS | Ethernet Port N Total Number of Received Bytes in Good Frames | 4603 A030h |
0003A034h | CPSW_STAT0_TXGOODFRAMES | Ethernet Port N Good Transmit Frames Register | 4603 A034h |
0003A038h | CPSW_STAT0_TXBROADCASTFRAMES | Ethernet Port N Broadcast Transmit Frames Register | 4603 A038h |
0003A03Ch | CPSW_STAT0_TXMULTICASTFRAMES | Ethernet Port N Multicast Transmit Frames Register | 4603 A03Ch |
0003A064h | CPSW_STAT0_TXOCTETS | Ethernet Port N Tx Octets Register | 4603 A064h |
0003A068h | CPSW_STAT0_OCTETFRAMES64 | Ethernet Port N 64 Octet Frames Register | 4603 A068h |
0003A06Ch | CPSW_STAT0_OCTETFRAMES65T127 | Ethernet Port N 65 to 127 Octet Frames Register | 4603 A06Ch |
0003A070h | CPSW_STAT0_OCTETFRAMES128T255 | Ethernet Port N 128 to 255 Octet Frames Register | 4603 A070h |
0003A074h | CPSW_STAT0_OCTETFRAMES256T511 | Ethernet Port N 256 to 511 Octet Frames Register | 4603 A074h |
0003A078h | CPSW_STAT0_OCTETFRAMES512T1023 | Ethernet Port N 512-pn_rx_maxlen Octet Frames Register | 4603 A078h |
0003A07Ch | CPSW_STAT0_OCTETFRAMES1024TUP | Ethernet Port N 1023-1518 Octet Frames Register | 4603 A07Ch |
0003A080h | CPSW_STAT0_NETOCTETS | Ethernet Port N Net Octets Register | 4603 A080h |
0003A084h | CPSW_STAT0_RX_BOTTOM_OF_FIFO_DROP | Ethernet Port N Receive Bottom of FIFO Drop Register | 4603 A084h |
0003A088h | CPSW_STAT0_PORTMASK_DROP | Ethernet Port N Portmask Drop Register | 4603 A088h |
0003A08Ch | CPSW_STAT0_RX_TOP_OF_FIFO_DROP | Ethernet Port N Receive Top of FIFO Drop Register | 4603 A08Ch |
0003A090h | CPSW_STAT0_ALE_RATE_LIMIT_DROP | Ethernet Port N ALE Rate Limit Drop Register | 4603 A090h |
0003A094h | CPSW_STAT0_ALE_VID_INGRESS_DROP | Ethernet Port N ALE VID Ingress Drop Register | 4603 A094h |
0003A098h | CPSW_STAT0_ALE_DA_EQ_SA_DROP | Ethernet Port N ALE DA equal SA Drop Register | 4603 A098h |
0003A09Ch | CPSW_STAT0_ALE_BLOCK_DROP | Ethernet Port N ALE Block Drop Register | 4603 A09Ch |
0003A0A0h | CPSW_STAT0_ALE_SECURE_DROP | Ethernet Port N ALE Secure Drop Register | 4603 A0A0h |
0003A0A4h | CPSW_STAT0_ALE_AUTH_DROP | Ethernet Port N ALE Authentication Drop Register | 4603 A0A4h |
0003A0A8h | CPSW_STAT0_ALE_UNKN_UNI | Ethernet Port N ALE Receive Unknown Unicast Register | 4603 A0A8h |
0003A0ACh | CPSW_STAT0_ALE_UNKN_UNI_BCNT | Ethernet Port N ALE Receive Unknown Unicast Bytecount Register | 4603 A0ACh |
0003A0B0h | CPSW_STAT0_ALE_UNKN_MLT | Ethernet Port N ALE Receive Unknown Multicast Register | 4603 A0B0h |
0003A0B4h | CPSW_STAT0_ALE_UNKN_MLT_BCNT | Ethernet Port N ALE Receive Unknown Multicast Bytecount Register | 4603 A0B4h |
0003A0B8h | CPSW_STAT0_ALE_UNKN_BRD | Ethernet Port N ALE Receive Unknown Broadcast Register | 4603 A0B8h |
0003A0BCh | CPSW_STAT0_ALE_UNKN_BRD_BCNT | Ethernet Port N ALE Receive Unknown Broadcast Bytecount Register | 4603 A0BCh |
0003A0C0h | CPSW_STAT0_ALE_POL_MATCH | Ethernet Port N ALE Policer Matched Register | 4603 A0C0h |
0003A0C4h | CPSW_STAT0_ALE_POL_MATCH_RED | Ethernet Port N ALE Policer Matched and Condition Red Register | 4603 A0C4h |
0003A0C8h | CPSW_STAT0_ALE_POL_MATCH_YELLOW | Ethernet Port N ALE Policer Matched and Condition Yellow Register | 4603 A0C8h |
0003A0CCh | CPSW_STAT0_ALE_MULT_SA_DROP | Enet Port N ALE Multicast Source Address Drop | 4603 A0CCh |
0003A0D0h | CPSW_STAT0_ALE_DUAL_VLAN_DROP | Enet Port N ALE Dual VLAN Drop | 4603 A0D0h |
0003A0D4h | CPSW_STAT0_ALE_LEN_ERROR_DROP | Enet Port N ALE IEEE 802.3 Length Error Drop | 4603 A0D4h |
0003A0D8h | CPSW_STAT0_ALE_IP_NEXT_HDR_DROP | Enet Port N ALE IP Next Header Limit Drop | 4603 A0D8h |
0003A0DCh | CPSW_STAT0_ALE_IPV4_FRAG_DROP | Enet Port N ALE IPv4 Fragment Drop | 4603 A0DCh |
0003A140h | CPSW_STAT0_IET_RX_ASSEMBLY_ERROR_REG | Enet Port N IET Received Assembly Error | 4603 A140h |
0003A144h | CPSW_STAT0_IET_RX_ASSEMBLY_OK_REG | Enet Port N IET Received Assembly OK | 4603 A144h |
0003A148h | CPSW_STAT0_IET_RX_SMD_ERROR_REG | Enet Port N IET Received SMD Error | 4603 A148h |
0003A14Ch | CPSW_STAT0_IET_RX_FRAG_REG | Enet Port N IET Received Fragment (IET fragment) | 4603 A14Ch |
0003A150h | CPSW_STAT0_IET_TX_HOLD_REG | Enet Port N IET Transmit Hold | 4603 A150h |
0003A154h | CPSW_STAT0_IET_TX_FRAG_REG | Enet Port N IET Transmit Fragment (IET fragment) | 4603 A154h |
0003A17Ch | CPSW_STAT0_TX_MEMORY_PROTECT_ERROR | Ethernet Port N Transmit Memory Protect CRC Error Register | 4603 A17Ch |
CPSW_STAT0_RXGOODFRAMES is shown in Figure 12-720 and described in Table 12-1376.
Return to Summary Table.
The total number of good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Had a length of 64 to SL_RX_MAXLEN[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the RX_ALIGN_CODE_ERRORS and CPSW_STAT0_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good frames received. |
CPSW_STAT0_RXBROADCASTFRAMES is shown in Figure 12-721 and described in Table 12-1378.
Return to Summary Table.
The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:
- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF
- Had a length of CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good broadcast frames received. |
CPSW_STAT0_RXMULTICASTFRAMES is shown in Figure 12-722 and described in Table 12-1380.
Return to Summary Table.
The total number of good multicast frames received on the port. A good multicast frame is defined to be:
- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF
- Had a length of CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good multicast frames received. |
CPSW_STAT0_RXCRCERRORS is shown in Figure 12-723 and described in Table 12-1382.
Return to Summary Table.
The total number of frames received on the port that experienced a CRC error. Such a frame:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was of length 64 to CPSW0_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no code/align error,
- Had a CRC error Overruns have no effect upon this statistic.
A CRC error is defined to be:
- A frame containing an even number of nibbles
- Failing the Frame Check Sequence test.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of CRC errors frames received. |
CPSW_STAT0_RXOVERSIZEDFRAMES is shown in Figure 12-724 and described in Table 12-1384.
Return to Summary Table.
The total number of oversized frames received on the port. An oversized frame is defined to be:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was greater than CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN in bytes
- Had no CRC error, alignment error or code error
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of oversized frames received. |
CPSW_STAT0_RXUNDERSIZEDFRAMES is shown in Figure 12-725 and described in Table 12-1386.
Return to Summary Table.
The total number of undersized frames received on the port. An undersized frame is defined to be:
- Was any data frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was less than 64 octets long
- Had no CRC error, alignment error or code error
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of undersized frames received. |
CPSW_STAT0_RXFRAGMENTS is shown in Figure 12-726 and described in Table 12-1388.
Return to Summary Table.
The total number of frame fragments received on the port. A frame fragment is defined to be:
- Any data frame (address matching does not matter)
- Less than 64 bytes long
- Having a CRC error, an alignment error, or a code error
- Not the result of a collision caused by half duplex, collision based flow control
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of fragmented frames received. |
CPSW_STAT0_ALE_DROP is shown in Figure 12-727 and described in Table 12-1390.
Return to Summary Table.
Total number of frames dropped by the ALE.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames dropped by the ALE. |
CPSW_STAT0_ALE_OVERRUN_DROP is shown in Figure 12-728 and described in Table 12-1392.
Return to Summary Table.
Total number of overrun frames dropped by the ALE.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A02Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of overrun frames dropped by the ALE. |
CPSW_STAT0_RXOCTETS is shown in Figure 12-729 and described in Table 12-1394.
Return to Summary Table.
The total number of bytes in all good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Of length 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error
See the CPSW_STAT0_RXCRCERRORS statistic descriptions for total number of CRC errors. Overruns have no effect upon this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of received bytes in good frames |
CPSW_STAT0_TXGOODFRAMES is shown in Figure 12-730 and described in Table 12-1396.
Return to Summary Table.
The total number of good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good frames transmitted |
CPSW_STAT0_TXBROADCASTFRAMES is shown in Figure 12-731 and described in Table 12-1398.
Return to Summary Table.
The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:
- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good broadcast frames transmitted. |
CPSW_STAT0_TXMULTICASTFRAMES is shown in Figure 12-732 and described in Table 12-1400.
Return to Summary Table.
The total number of good multicast frames received on the port. A good multicast frame is defined to be:
- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A03Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of good multicast frames transmitted. |
CPSW_STAT0_TXOCTETS is shown in Figure 12-733 and described in Table 12-1402.
Return to Summary Table.
The total number of bytes in all good frames transmitted on the port. A good frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Was any size
- Had no late or excessive collisions, no carrier loss and no underrun.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of bytes in all good frames transmitted |
CPSW_STAT0_OCTETFRAMES64 is shown in Figure 12-734 and described in Table 12-1404.
Return to Summary Table.
The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was exactly 64 bytes long. (If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted, then the frame will be recorded in this statistic).
CRC errors, code/align errors and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of 64-byte frames received and transmitted |
CPSW_STAT0_OCTETFRAMES65T127 is shown in Figure 12-735 and described in Table 12-1406.
Return to Summary Table.
The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 65 to 127 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A06Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 65 to 127 bytes received and transmitted |
CPSW_STAT0_OCTETFRAMES128T255 is shown in Figure 12-736 and described in Table 12-1408.
Return to Summary Table.
The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 128 to 255 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 128 to 255 bytes received and transmitted |
CPSW_STAT0_OCTETFRAMES256T511 is shown in Figure 12-737 and described in Table 12-1410.
Return to Summary Table.
The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 256 to 511 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 256 to 511 bytes received and transmitted. |
CPSW_STAT0_OCTETFRAMES512T1023 is shown in Figure 12-738 and described in Table 12-1412.
Return to Summary Table.
The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 512 to 1023 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 512 to 1023 bytes received and transmitted. |
CPSW_STAT0_OCTETFRAMES1024TUP is shown in Figure 12-739 and described in Table 12-1414.
Return to Summary Table.
The total number of frames of size 1024 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 1024 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes long on receive, or any size on transmit
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A07Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 1024 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes received and 1024 bytes or greater transmitted. |
CPSW_STAT0_NETOCTETS is shown in Figure 12-740 and described in Table 12-1416.
Return to Summary Table.
The total number of bytes of frame data received and transmitted on the port. Each frame counted:
- was any data or MAC control frame destined for any unicast, broadcast or multicast address (address match does not matter)
- Any length (including less than 64 bytes and greater than CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes)
Also counted in this statistic is:
- Every byte transmitted before a carrier- loss was experienced
- Every byte transmitted before each collision was experienced, (i.e. multiple retries are counted each time)
- Every byte received if the port is in half-duplex mode until a jam sequence was transmitted to initiate flow control. (The jam sequence was not counted to prevent double-counting)
Error conditions such as alignment errors, CRC errors, code errors, overruns and underruns do not affect the recording of bytes by this statistic. The objective of this statistic is to give a reasonable indication of ethernet utilization
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of bytes received and transmitted |
CPSW_STAT0_RX_BOTTOM_OF_FIFO_DROP is shown in Figure 12-741 and described in Table 12-1418.
Return to Summary Table.
Receive Bottom of FIFO Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Receive Bottom of FIFO Drop. |
CPSW_STAT0_PORTMASK_DROP is shown in Figure 12-742 and described in Table 12-1420.
Return to Summary Table.
Total number of dropped frames received due to portmask.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames received due to portmask. |
CPSW_STAT0_RX_TOP_OF_FIFO_DROP is shown in Figure 12-743 and described in Table 12-1422.
Return to Summary Table.
Receive Top of FIFO Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A08Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Receive Top of FIFO Drop. |
CPSW_STAT0_ALE_RATE_LIMIT_DROP is shown in Figure 12-744 and described in Table 12-1424.
Return to Summary Table.
Total number of dropped frames due to ALE Rate Limiting.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Rate Limiting. |
CPSW_STAT0_ALE_VID_INGRESS_DROP is shown in Figure 12-745 and described in Table 12-1426.
Return to Summary Table.
Total number of dropped frames due to ALE VID Ingress.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE VID Ingress. |
CPSW_STAT0_ALE_DA_EQ_SA_DROP is shown in Figure 12-746 and described in Table 12-1428.
Return to Summary Table.
Total number of dropped frames due to DA=SA.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to DA=SA. |
CPSW_STAT0_ALE_BLOCK_DROP is shown in Figure 12-747 and described in Table 12-1430.
Return to Summary Table.
Total number of dropped frames due to ALE Block Mode.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A09Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Block Mode. |
CPSW_STAT0_ALE_SECURE_DROP is shown in Figure 12-748 and described in Table 12-1432.
Return to Summary Table.
Total number of dropped frames due to ALE Secure Mode.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Secure Mode. |
CPSW_STAT0_ALE_AUTH_DROP is shown in Figure 12-749 and described in Table 12-1434.
Return to Summary Table.
Total number of dropped frames due to ALE Authentication.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Authentication. |
CPSW_STAT0_ALE_UNKN_UNI is shown in Figure 12-750 and described in Table 12-1436.
Return to Summary Table.
ALE Receive Unknown Unicast.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Unicast. |
CPSW_STAT0_ALE_UNKN_UNI_BCNT is shown in Figure 12-751 and described in Table 12-1438.
Return to Summary Table.
ALE Receive Unknown Unicast Bytecount.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Unicast Bytecount. |
CPSW_STAT0_ALE_UNKN_MLT is shown in Figure 12-752 and described in Table 12-1440.
Return to Summary Table.
ALE Receive Unknown Multicast.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Multicast. |
CPSW_STAT0_ALE_UNKN_MLT_BCNT is shown in Figure 12-753 and described in Table 12-1442.
Return to Summary Table.
ALE Receive Unknown Multicast Bytecount.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Multicast Bytecount. |
CPSW_STAT0_ALE_UNKN_BRD is shown in Figure 12-754 and described in Table 12-1444.
Return to Summary Table.
ALE Receive Unknown Broadcast.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Broadcast. |
CPSW_STAT0_ALE_UNKN_BRD_BCNT is shown in Figure 12-755 and described in Table 12-1446.
Return to Summary Table.
ALE Receive Unknown Broadcast Bytecount.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Broadcast Bytecount. |
CPSW_STAT0_ALE_POL_MATCH is shown in Figure 12-756 and described in Table 12-1448.
Return to Summary Table.
ALE Policer Matched.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched. |
CPSW_STAT0_ALE_POL_MATCH_RED is shown in Figure 12-757 and described in Table 12-1450.
Return to Summary Table.
ALE Policer Matched and Condition Red.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched and Condition Red. |
CPSW_STAT0_ALE_POL_MATCH_YELLOW is shown in Figure 12-758 and described in Table 12-1452.
Return to Summary Table.
ALE Policer Matched and Condition Yellow.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched and Condition Yellow. |
CPSW_STAT0_ALE_MULT_SA_DROP is shown in Figure 12-759 and described in Table 12-1454.
Return to Summary Table.
ALE Multicast Source Address Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Multicast Source Address drop. |
CPSW_STAT0_ALE_DUAL_VLAN_DROP is shown in Figure 12-760 and described in Table 12-1456.
Return to Summary Table.
ALE Dual VLAN Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Dual VLAN drop. |
CPSW_STAT0_ALE_LEN_ERROR_DROP is shown in Figure 12-761 and described in Table 12-1458.
Return to Summary Table.
ALE Length Error Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Length Error drop. |
CPSW_STAT0_ALE_IP_NEXT_HDR_DROP is shown in Figure 12-762 and described in Table 12-1460.
Return to Summary Table.
ALE IP Next Header Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0D8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE Next Header drop. |
CPSW_STAT0_ALE_IPV4_FRAG_DROP is shown in Figure 12-763 and described in Table 12-1462.
Return to Summary Table.
ALE IPV4 Frag Drop.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A0DCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | ALE IPV4 Fragment drop. |
CPSW_STAT0_IET_RX_ASSEMBLY_ERROR_REG is shown in Figure 12-764 and described in Table 12-1464.
Return to Summary Table.
IET Receive Assembly Error.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_RX_ASSEMBLY_ERROR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_RX_ASSEMBLY_ERROR | R/W | 0h | IET Receive Assembly Error Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_IET_RX_ASSEMBLY_OK_REG is shown in Figure 12-765 and described in Table 12-1466.
Return to Summary Table.
IET Receive Assembly Ok.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A144h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_RX_ASSEMBLY_OK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_RX_ASSEMBLY_OK | R/W | 0h | IET Receive Assembly Ok. Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_IET_RX_SMD_ERROR_REG is shown in Figure 12-766 and described in Table 12-1468.
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IET Receive Smd Error.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A148h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_RX_SMD_ERROR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_RX_SMD_ERROR | R/W | 0h | IET Receive Smd Error. Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_IET_RX_FRAG_REG is shown in Figure 12-767 and described in Table 12-1470.
Return to Summary Table.
IET Receive Frag.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A14Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_RX_FRAG | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_RX_FRAG | R/W | 0h | IET Receive Frag. Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_IET_TX_HOLD_REG is shown in Figure 12-768 and described in Table 12-1472.
Return to Summary Table.
IET Transmit Hold.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A150h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_TX_HOLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_TX_HOLD | R/W | 0h | IET Transmit Hold.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_IET_TX_FRAG_REG is shown in Figure 12-769 and described in Table 12-1474.
Return to Summary Table.
IET Transmit Frag.
Note: IET functionallity is not supported for MCU_CPSW0 Port 0.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A154h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IET_TX_FRAG | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | IET_TX_FRAG | R/W | 0h | IET Transmit Frag. Note: IET functionallity is not supported for MCU_CPSW0 Port 0. |
CPSW_STAT0_TX_MEMORY_PROTECT_ERROR is shown in Figure 12-770 and described in Table 12-1476.
Return to Summary Table.
Transmit Memory Protect CRC Error.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_STAT0 | 4603 A17Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | COUNT | R/W | 0h | Transmit Memory Protect CRC Error. Note: If there is a memorry protect error, then this COUNT value will increment and issue a STAT_PEND0 interrupt, when this bit field is non-zero. That is different from the other stats which only issue an interrupt when their values are greater than 0xFFFF. |