The L1D cache supports 2 data paths that service one DSP core. The data path connected to the DSPs scalar side is 64 bits wide while the one connect to the vector side is configurable and matches the CPU vector width. The L1D controls a 2-way cache and is also connected to the unified memory controller (UMC) which is then connected to the rest of the DSP system.
The L1D memory system provides the following key features:
- L1 data memory controller (DMC) with 64 KB L1D memory, configurable as cache
- L1D cache
- Dual data path
- 64-bit and 256-bit data paths
- 64-byte cache line size
- Read-allocate cache
- Write-through cache for L2/EL2 accesses
- Physically Indexed, Physically Tagged
- LRU replacement policy
- Non-aligned access support
- Hit under Miss
- FENCE operation on outstanding transactions with support for two types of transactions
- Atomic operation support - C7x and RISC-V opcodes
- ECR access from the CPU. Accessed with a CPU MVC instruction
- 320-bit/cycle (256+64) bandwidth to/from the DSP core
- 256-bit/cycle RAM bandwidth
- 256-bit/cycle bandwidth to UMC and bandwidth
- Per byte ECC Protection od data stored in the cache
- 1 parity bit per tag entry