SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
AET Status Register This register provides access to AET Status
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 1008h |
| C7X256V1_DEBUG | 0007 3800 1008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| BEND | TEND | RESERVED_3 | UDF | ||||
| R | R | R/W | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIG | REND | RESERVED_2 | |||||
| R | R | R/W | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_2 | SMM | ST | |||||
| R/W | R | R | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ST | RESERVED | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | BEND | R | 0h | A status bit set to a one by a qualified version of trigger that stops the CPU [qualified by FUNC_CNTL:BPE, FUNC_CNTL:BPC, and CPU State] Reset to a zero by Writing a one to IAR_ADD:RBEND A simultaneous set and reset condition causes the bit to be set Read 0: Indicates that a breakpoint trigger has not been generated recently Read 1: Indicates that a breakpoint trigger was recently encountered |
| 30 | TEND | R | 0h | Trace End Status A status bit set to a one by the trace end trigger Reset to a zero by a Writing a one to IAR_ADD:RTEND A simultaneous set and reset condition causes the bit to be set Read 0: Indicates that a trace end trigger has not been generated recently Read 1: Indicates that a trace end trigger was recently encountered |
| 29:28 | RESERVED_3 | R/W | 0h | reserved |
| 27:24 | UDF | R | 0h | Counter Underflow Status The meaning of this field depend on the counter operating mode Generic Operating Mode This flag is set to a one when the counter specified by the index n is directed to count past zero to the maximum counter value Reset to a zero by Writing a one to IAR_ADD:RUDF[n] or by disabling the counter A simultaneous set and reset condition causes this bit to be set Watermark Operating Mode The UDF[n] flag is set to a one when the counter specified by the index n is directed to count past zero to the maximum counter value Reset to a zero by Writing a one to IAR_ADD:RUDF[n] or by disabling the counter A simultaneous set and reset condition causes this bit to be set The UDF[n+1] flag is set to a one when a watermark window is terminated [eg end trigger is acted on] Reset to a zero by a Writing a one to IAR_ADD:RUDF[n+1] or by disabling the counter A simultaneous set and reset condition causes this bit to be set |
| 23 | TRIG | R | 0h | Trace Trigger A status bit set to one by the trace trigger Reset to a zero by Writing a one to IAR_ADD:RTEND A simultaneous set and reset condition causes this bit to be set |
| 22 | REND | R | 0h | AET Interrupt Status A status bit set to a one by a qualified version of the CPU_INT trigger [qualified by FUNC_CNTL:RIE, FUNC_CNTL:RIC, and CPU State] Reset to a zero by Writing a one to IAR_ADD:RREND A simultaneous set and reset condition causes this bit to be set |
| 21:10 | RESERVED_2 | R/W | 0h | reserved |
| 9 | SMM | R | 0h | State Machine Mode This bit shadows the FUNC_CNTL:SMM bit-field |
| 8:5 | ST | R | 0h | State Machine Current State SMM ST Encoding - 0000 State Machine not enabled 0 0001 State 0 0 0010 State 1 0 0100 State 2 0 1000 State 3 1 --01 State 0 [Machine 0] 1 --10 State 1 [Machine 0] 1 01-- State 0 [Machine 1] 1 10-- State 1 [Machine 1] |
| 4:0 | RESERVED | R/W | 0h | reserved |