SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls various parameters of the cotroller state.
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC1 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | HW_RW_DELAY_COUNT | ||||||
| NONE | R/W | ||||||
| 0h | Ah | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HW_RW_DELAY_COUNT | HW_RW_DELAY_EN | DP_EN | OSPI_32B_DISABLE_MODE | ||||
| R/W | R/W | R/W | R/W | ||||
| Ah | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DISXIP | OSPI_DDR_DISABLE_MODE | RESERVED | ECC_DISABLE_ADR | FSS_AES_EN_IPCFG | RESERVED | ECC_EN | |
| R/W | R/W | NONE | R/W | R | NONE | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18:11 | HW_RW_DELAY_COUNT | R/W | Ah | Delay for switching between reads and writes Reset Source: vbus_mod_g_rst_n |
| 10 | HW_RW_DELAY_EN | R/W | 0h | Enable delay when switching between reads and writes to avoid read-write collision for sensitive logic. Reset Source: vbus_mod_g_rst_n |
| 9 | DP_EN | R/W | 0h | 0 Safety double pumping disabled. 1 Safety double pumping enabled Reset Source: vbus_mod_g_rst_n |
| 8 | OSPI_32B_DISABLE_MODE | R/W | 0h | 0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled Reset Source: vbus_mod_g_rst_n |
| 7 | DISXIP | R/W | 0h | This field is used to disable XIP prefetching. 0 XIP Prefetch Enabled. 1 XIP prefetch disabled Please note that this is referring to prefetching feature that is useful for linear accesses associated with XIP. This is NOT referring to XIP features implemented in flash Controller or memory device. Reset Source: vbus_mod_g_rst_n |
| 6 | OSPI_DDR_DISABLE_MODE | R/W | 0h | 0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled Reset Source: vbus_mod_g_rst_n |
| 5:4 | RESERVED | NONE | 0h | Reserved |
| 3 | ECC_DISABLE_ADR | R/W | 0h | 0 Block address within ECC calculation, 1 Block address not within ECC calculation Reset Source: vbus_mod_g_rst_n |
| 2 | FSS_AES_EN_IPCFG | R | 0h | 1 select security, 0 disable security Reset Source: vbus_mod_g_rst_n |
| 1 | RESERVED | NONE | 0h | Reserved |
| 0 | ECC_EN | R/W | 0h | 0 ECC disabled. 1 ECC enabled Reset Source: vbus_mod_g_rst_n |