SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 2024h |
| C7X256V1_DEBUG | 0007 3800 2024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESET | FLUSH | TRIGGER_EN | ENABLE | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | R/W | 0h | reserved |
| 3 | RESET | R/W | 0h | Writing a 1 to this bit will initiate a reset of read and write synchronous FIFO pointers and will disable the export module by clearing all writable bits in this register and updating the Trace Export Status register bits to their reset state The bit will reset automatically to a 0 after the reset has been completed and will read as 1 whilst the reset is ongoing |
| 2 | FLUSH | R/W | 0h | Writing a 1 to this bit will initiate an internal trace flush This bit reads as 1 until the initiated flush is completed |
| 1 | TRIGGER_EN | R/W | 0h | Writing a 1 to this bit shall enable embedded triggers to be inserted into the ATB data stream |
| 0 | ENABLE | R/W | 0h | When written with a 1, this is a request to enable trace export and acquisition from the PLF interface When written with a 0, this is a request to disable trace export This also requests disablement of collection of new trace data from the PLF interface since it cannot be exported This is equivalent of clearing AET triggers and not allowing collection of trace data When read as a 1, this means trace export has been requested to be enabled or is enabled When read as a 0, this means trace export has been requested to be disabled or is disabled Trace Export may be confirmed as disabled by waiting for the HALTED bit to go from 0->1 The Trace FIFO is confirmed as empty when the DRAIN_DONE bit is set |