SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_14 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_14 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_14 | CME | RESERVED_12 | EU3S | EWE | CRS | CSS | |
| R | R/W | R | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LHCRST | RESERVED_6_4 | HSEE | INTE | HCRST | R_S | ||
| R/W | R | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:14 | RESERVED_31_14 | R | 0h | Reserved |
| 13 | CME | R/W | 0h | CEM Enable For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 12 | RESERVED_12 | R | 0h | Reserved |
| 11 | EU3S | R/W | 0h | EU3S For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 10 | EWE | R/W | 0h | EWE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 9 | CRS | R/W | 0h | Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1', the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore process, it sets DSTS.RSS to '0'. Note: When read, this field always returns '0'. Reset Source: rst_mod_g_rst_n |
| 8 | CSS | R/W | 0h | Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1', the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process, it sets DSTS.SSS to '0'. Note: When read, this field always returns '0'. Reset Source: rst_mod_g_rst_n |
| 7 | LHCRST | R/W | 0h | Light Host Controller Reset For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail [Timeout]. - HCRST - LHCRST Bit Bash register testing is not recommended. Reset Source: rst_mod_g_rst_n |
| 6:4 | RESERVED_6_4 | R | 0h | Reserved |
| 3 | HSEE | R/W | 0h | HSEE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 2 | INTE | R/W | 0h | INTE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 1 | HCRST | R/W | 0h | HCRST The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail [Timeout]. - HCRST - LHCRST Bit Bash register testing is not recommended. Reset Source: rst_mod_g_rst_n |
| 0 | R_S | R/W | 0h | R_S For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing. Reset Source: rst_mod_g_rst_n |