SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Read Only Mirror of MCU CTRL MMR version. After an MCU_PORz reset this bit field resets to 0x00000000. While this bit field remains 0x00000000 any warm reset from the Main Domain also propagates through the MCU domain. If the application does not require reset isolation of the MCU domain, it may leave this bit field with a value of 0x00000000. If the application does require reset isolation of the MCU domain after the initial boot, then the R5FSS CPU must write a nonzero value to the magic word. The actual value is left to software and different values may be used to convey information, but in order to isolate the MCU domain from all Main domain warm reset sources that trigger main_resetz, the value must be non-zero. If the value is nonzero and one of the Main domain warm reset sources triggers main_resetz occurs in the main domain, the R5FSS will not be reset. The Main domain bootloader must read this value to determine that the R5FSS is already initialized, and has configured reset isolation. The Main domain bootloader then also skips any initialization steps involving bootstrapping the R5FSS as it is is already running. Note that MCU_PORz reset is never blocked by a nonzero magic word.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 817Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RST_MAGIC_WORD_MCU_MAGIC_WORD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RST_MAGIC_WORD_MCU_MAGIC_WORD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RST_MAGIC_WORD_MCU_MAGIC_WORD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RST_MAGIC_WORD_MCU_MAGIC_WORD | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | RST_MAGIC_WORD_MCU_MAGIC_WORD | R | 0h | Magic Word Indicating Status of MCU Subsystem Boot Reset Source: main_chip1_rst_n |