SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The L2 High address Least Significant word defines the least significant portion of the high cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when ~ienable is set.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0018h |
| RL2_0 | 2500 1018h |
| RL2_2 | 2500 2018h |
| RL2_3 | 2500 3018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDRESS_HI_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDRESS_HI_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDRESS_HI_LSW | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:11 | ADDRESS_HI_LSW | R/W | 0h | The ~iaddress_hi_lsw defines the high address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be ones. |
| 10:0 | RESERVED | NONE | 0h | Reserved |