SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Link Setting Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 D020h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31 | U1_RESID_TIMER_US | RESERVED_27 | PM_LC_TIMER_US | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 4h | 0h | 5h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PM_ENTRY_TIMER_US | RESERVED_0_19 | ||||||
| R/W | R/W | ||||||
| 9h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_0_19 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_0_19 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_31 | R/W | 0h | Reserved |
| 30:28 | U1_RESID_TIMER_US | R/W | 4h | Programmable U1 MIN RESIDENCY TIMER This field specifies U1 MIN RESIDENCY TIMER value in us. Set to 0 to disable the timer. Reset Source: rst_mod_g_rst_n |
| 27 | RESERVED_27 | R/W | 0h | Reserved |
| 26:24 | PM_LC_TIMER_US | R/W | 5h | Programmable PM_LC_TIMER This field specifies PM_LC_TIMER value in us. Reset Source: rst_mod_g_rst_n |
| 23:20 | PM_ENTRY_TIMER_US | R/W | 9h | Programmable PM_ENTRY_TIMER This field specifies PM_ENTRY_TIMER value in us. Reset Source: rst_mod_g_rst_n |
| 19:0 | RESERVED_0_19 | R/W | 0h | Reserved |