SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
STP Synchronization Control Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 9810h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EXPMODE | COUNT | |||||
| R | R/W | R/W | |||||
| 0h | 1h | 30Ch | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COUNT | |||||||
| R/W | |||||||
| 30Ch | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | R | 0h | Reserved, returns 0 |
| 12 | EXPMODE | R/W | 1h | Exponent mode, A value of 1 sets count to 2 to the Nth, where Nth is ((bits 11 : 8)+12). A value of 0 sets Count to N (bits 11 : 0) |
| 11:0 | COUNT | R/W | 30Ch | The number of bytes between Synchronization packets |