SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Trace Trigger Control and Status Register The trace trigger control and status registers may be used to enable or disable trace data capture in the PC, Timing or Data Trace Streams without touching the AET module. The trigger registers may also be used in conjunction with AET to provide additional resources for trigger generation. When trigger register chaining mode is enabled in the trace ctrl register, software must follow this sequence: Write to TRC_TRIG0_CNTL_STAT register which does not immediately take effect Write to TRC_TRIG1_CNTL_STAT register which results in a 64-bit write taking effect to include the last update to TRC_TRIG1_CNTL_STAT register. The status bits in both of the trigger control and status registers when indicating that a trace capture window is not active do not account for effects such as: Flushing partial branch bits packets PRELIMINARY documents contain information on a product under development and are issued for evaluation purposes only. Features, characteristic data and other information are subject to change. TI Confidential NDA Restrictions UNDER NON DISCLOSURE AGREEMENT. DO NOT COPY. Page 171 of 188 Flushing read data scoreboard Flushing partial timing packets Flushing partial event trace packets Generating Sync Points that are required due to one or more trace streams being disabled The status bit only indicates that a trace capture window is being disabled. The status bits account for all parameters required to decide if a capture window is open or not: AET triggers Application triggers Security PLF conditions (i.e. foreground or background code execution or halted status) Trace Stream Enables Trace Enable bit in the Trace Export Control Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 2018h |
| C7X256V1_DEBUG | 0007 3800 2018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TRACE_TRIG | TRACE_END | TRACE_NO_STORE_SBPT_LE | TRACE_NO_STORE_SBPT | TRACE_NO_STORE_DATA_LE | TRACE_NO_STORE_DATA | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RESERVED | R/W | 0h | reserved |
| 5 | TRACE_TRIG | R/W | 0h | Write 1: This bit shall generate a pulse on Trace Trigger Write 0 : No effect |
| 4 | TRACE_END | R/W | 0h | Write 1: This bit shall generate a pulse on Trace End Trigger Write 0 : No effect |
| 3 | TRACE_NO_STORE_SBPT_LE | R/W | 0h | Load Enable for TRACE_NO_STORE_SBPT Write 1: Allows TRACE_NO_STORE_SBPT field to be updated with the value presented to that field Write 0: No effect |
| 2 | TRACE_NO_STORE_SBPT | R/W | 0h | Write 0/1: This bit updates level of TRACE_NO_STORE_SBPT trigger when the next higher bit is set Read 0: SPBT trace capture window is active for data trace stream Read 1: SPBT trace capture is not active for the data trace stream or is being disabled |
| 1 | TRACE_NO_STORE_DATA_LE | R/W | 0h | Load Enable for TRACE_NO_STORE_DATA Write 1: Allows TRACE_NO_STORE_DATA field to be updated with the value presented to that field Write 0: No effect |
| 0 | TRACE_NO_STORE_DATA | R/W | 0h | Write 0/1: This bit updates level of TRACE_NO_STORE_DATA trigger when the next higher bit is set Read 0: Data trace capture window is active for either of RA,WA,RD,WD Read 1: Data trace capture window is not active for any of RA,WA,RD,WD or is being disabled |