SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Register AFE_BC_REG5
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 80A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BC_ANA_REG5 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | BC_ANA_REG5 | R/W | 0h | Bit 0= 0- Do not overdrive ID comparator output, 1- Overdrive ID comparator output. Bit 1= 0 Do not overdrive VBUS_DIV signal, 1- Overdrive VBUS_DIV signal. Bit 2= 0- VBUS_DIV signal low, 1- VBUS_DIV signal high. Bits 7:3= reserved. Reset Source: usb2_sync_preset_n |