SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus Instances and presence of Debug Capability. device mode requires only one RxFIFO. The register default values for each mode are assigned in coreConsultant based on the maximum packet size, number of packets to be buffered, speed of the host bus instance, bus latency, and mode of operation (host, device, or DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values. For the debug capability mode, the currently mapped RxFIFO number can be read from the GFIFOPRIDBC register. For more details on the usage of the GTXFIFOSIZn and GRXFIFOSIZn registers for different modes of operation, refer to "Memory Requirements" chapter in the Databook.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C380h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RXFSTADDR_N | |||||||
| R/W | |||||||
| 38Ah | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RXFSTADDR_N | |||||||
| R/W | |||||||
| 38Ah | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RXFDEP_N | |||||||
| R/W | |||||||
| 209h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RXFDEP_N | |||||||
| R/W | |||||||
| 209h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RXFSTADDR_N | R/W | 38Ah | RxFIFOn RAM Start Address [RxFStAddr_n] This field contains the memory start address for RxFIFOn in MDWIDTH-bit words. Reset Source: rst_mod_g_rst_n |
| 15:0 | RXFDEP_N | R/W | 209h | RxFIFO Depth [RxFDep_n] This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16,384 Reset Source: rst_mod_g_rst_n |