SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Offset | Length | Register Name | CPSW0 Physical Address |
|---|---|---|---|
| 0h | 32 | CPSW3_ECC_ECC_REV | 0070 4000h + formula |
| 8h | 32 | CPSW3_ECC_ECC_VECTOR | 0070 4008h + formula |
| Ch | 32 | CPSW3_ECC_ECC_STAT | 0070 400Ch + formula |
| 10h | 32 | CPSW3_ECC_ECC_RESERVED_SVBUS_J | 0070 4010h + formula |
| 3Ch | 32 | CPSW3_ECC_ECC_SEC_EOI_REG | 0070 403Ch + formula |
| 40h | 32 | CPSW3_ECC_ECC_SEC_STATUS_REG0 | 0070 4040h + formula |
| 80h | 32 | CPSW3_ECC_ECC_SEC_ENABLE_SET_REG0 | 0070 4080h + formula |
| C0h | 32 | CPSW3_ECC_ECC_SEC_ENABLE_CLR_REG0 | 0070 40C0h + formula |
| 13Ch | 32 | CPSW3_ECC_ECC_DED_EOI_REG | 0070 413Ch + formula |
| 140h | 32 | CPSW3_ECC_ECC_DED_STATUS_REG0 | 0070 4140h + formula |
| 180h | 32 | CPSW3_ECC_ECC_DED_ENABLE_SET_REG0 | 0070 4180h + formula |
| 1C0h | 32 | CPSW3_ECC_ECC_DED_ENABLE_CLR_REG0 | 0070 41C0h + formula |
| 200h | 32 | CPSW3_ECC_ECC_AGGR_ENABLE_SET | 0070 4200h + formula |
| 204h | 32 | CPSW3_ECC_ECC_AGGR_ENABLE_CLR | 0070 4204h + formula |
| 208h | 32 | CPSW3_ECC_ECC_AGGR_STATUS_SET | 0070 4208h + formula |
| 20Ch | 32 | CPSW3_ECC_ECC_AGGR_STATUS_CLR | 0070 420Ch + formula |