SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG1_INIT parameter) because the standard xHCI driver does not access this register. For more details on this register, refer to "System Bus Interface" section in the Databook.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_13 | EN1KPAGE | PIPETRANSLIMIT | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 3h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_7_0 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED_31_13 | R | 0h | Reserved |
| 12 | EN1KPAGE | R/W | 0h | 1k Page Boundary Enable By default [this bit is disabled] the AXI breaks transfers at the 4k page boundary. When this bit is enabled, the AXI initiator [DMA data] breaks transfers at the 1k page boundary. Reset Source: rst_mod_g_rst_n |
| 11:8 | PIPETRANSLIMIT | R/W | 3h | AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI initiator pushes to the AXI target. When the AXI initiator reaches this limit, it does not make any more requests on the AXI ARADDR and AWADDR buses until the associated data phases complete. This field is encoded as follows: - 'h0: 1 request - 'h1: 2 requests - 'h2: 3 requests - 'h3: 4 requests - ... - 'hF: 16 requests Reset Source: rst_mod_g_rst_n |
| 7:0 | RESERVED_7_0 | R | 0h | Reserved |