SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0014h |
| UART1 | 0281 0014h |
| UART2 | 0282 0014h |
| UART3 | 0283 0014h |
| UART4 | 0284 0014h |
| UART5 | 0285 0014h |
| UART6 | 0286 0014h |
| WKUP_UART0 | 2B30 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_FIFO_STS | TX_SR_E | TX_FIFO_E | RX_BI | RX_FE | RX_PE | RX_OE | RX_FIFO_E |
| R | R | R | R | R | R | R | R |
| 0h | 1h | 1h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | RX_FIFO_STS | R | 0h | 0 Normal operation
1 At least one parity error, framing error or
break indication in the RX FIFO. Bit 7 is
cleared when no more errors are present in
the RX FIFO. |
| 6 | TX_SR_E | R | 1h | 0 Transmitter hold (TX FIFO) and shift
registers are not empty.
1 Transmitter hold (TX FIFO) and shift
registers are empty |
| 5 | TX_FIFO_E | R | 1h | 0 Transmit hold register (TX FIFO) is not
empty
1 Transmit hold register (TX FIFO) is empty.
The transmission is not necessarily
completed. |
| 4 | RX_BI | R | 0h | 0 No break condition
1 A break was detected while the data being
read from the RX FIFO was being received.
(i.e. RX input was low for one character +
1 bit time frame). |
| 3 | RX_FE | R | 0h | 0 No framing error in data being read from RX
FIFO.
1 Framing error occurred in data being read
from RX FIFO.(received data did not have a
valid stop bit) |
| 2 | RX_PE | R | 0h | 0 No parity error in data being read from RX
FIFO.
1 Parity error in data being read from RX
FIFO |
| 1 | RX_OE | R | 0h | 0 No overrun error
1 Overrun error has occurred. Set when the
character held in the receive shift
register is not transferred to the RX FIFO.
This case can occurs only when receive FIFO
is full. |
| 0 | RX_FIFO_E | R | 0h | 0 No data in the receive FIFO 1 At least one data character in the RX FIFO |