SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Memory Address Register 0
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0040h |
| C7X256V1_DEBUG | 0007 3800 0040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ADDR0 | R/W | 0h | Low order address bits for designating the target of an indirect debug access This bit field holds the 32 LSBs of the address of an indirect debug port transaction If the port is set for auto-incrementing addresses [DBG_INDRCT_CNTL:MEM_INC_ADDR = 1], this field will be incremented by the access size each time a transaction completes |