SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The L2 HIT Counter register holds the number of L2 Hits to the Remote data storage memory.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0078h |
| RL2_0 | 2500 1078h |
| RL2_2 | 2500 2078h |
| RL2_3 | 2500 3078h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| HIT | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| HIT | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HIT | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HIT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | HIT | R/W | 0h | The ~ihit Counts the number of hits to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over, it will stop counting at all ones. |