SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indicates LBIST status and provides MISR selection control
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 C018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| R5SS0_LBIST_STAT_BIST_DONE | RESERVED | ||||||
| R | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R5SS0_LBIST_STAT_BIST_RUNNING | RESERVED | R5SS0_LBIST_STAT_OUT_MUX_CTL | |||||
| R | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R5SS0_LBIST_STAT_MISR_MUX_CTL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | R5SS0_LBIST_STAT_BIST_DONE | R | 0h | LBIST is done Reset Source: mod_g_rst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15 | R5SS0_LBIST_STAT_BIST_RUNNING | R | 0h | LBIST is running Reset Source: mod_g_rst_n |
| 14:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | R5SS0_LBIST_STAT_OUT_MUX_CTL | R/W | 0h | Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value Reset Source: mod_g_rst_n |
| 7:0 | R5SS0_LBIST_STAT_MISR_MUX_CTL | R/W | 0h | Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR. Reset Source: mod_g_rst_n |