SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to enable the normal interrupt status register fields
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0034h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| BIT15_FIXED0 | BOOT_COMPLETE | RCV_BOOT_ACK | RETUNING_EVENT | INTC | INTB | INTA | CARD_INTERRUPT |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CARD_REMOVAL | CARD_INSERTION | BUF_RD_READY | BUF_WR_READY | DMA_INTERRUPT | BLK_GAP_EVENT | XFER_COMPLETE | CMD_COMPLETE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | BIT15_FIXED0 | R | 0h | The HC shall control error Interrupts using the Error Interrupt Status Enable register. Reset Source: vbus_amod_g_rst_n |
| 14 | BOOT_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 13 | RCV_BOOT_ACK | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 12 | RETUNING_EVENT | R/W | 0h |
0 - Masked
1 - Enabled
1 0 |
| 11 | INTC | R/W | 0h |
If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
1 0 |
| 10 | INTB | R/W | 0h |
If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
1 0 |
| 9 | INTA | R/W | 0h |
If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
1 0 |
| 8 | CARD_INTERRUPT | R/W | 0h |
If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.
By setting this bit to 0, interrupt input should be masked by implementation so that the interrupt Input is not affected by external signal in any state [ex. floating].
1 0 |
| 7 | CARD_REMOVAL | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 6 | CARD_INSERTION | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 5 | BUF_RD_READY | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 4 | BUF_WR_READY | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 3 | DMA_INTERRUPT | R/W | 0h |
'0' Masked,
'1' Enabled
1 0 |
| 2 | BLK_GAP_EVENT | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 1 | XFER_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |
| 0 | CMD_COMPLETE | R/W | 0h |
'0' Masked
'1' Enabled
1 0 |