SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls operation of the RL2 Cache Controller for Main R5 Cluster0 Core1. Note this register has no effect if Main R5 Cluster0 is operating in lockstep mode.
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 4764h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | R5SS0_CORE1_RL2_CTRL_RTXIP_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | R5SS0_CORE1_RL2_CTRL_RTXIP_SEL | R/W | 0h | Selects R5SS0 Core 1 OSPI0 XIP realtime access mode When realtime accesses are enabled, read transactions take priority over write transactions. This prevents XIP delays when Flash RWW updates are active. Field values (others are reserved): 2'b00 - No realtime accesses 2'b01 - Realtime access on RL2 Flash read pending 2'b10 - All read accesses are realtime Reset Source: mod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |