SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Device Event Enable Register This register controls the generation of device-specific events (see "Event Buffer Content for Device-Specific Events (DEVT)" section). If an enable bit is set to 0, the event will not be generated.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C708h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_17 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_17 | ECCERREN | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15 | L1WKUPEVTEN | RESERVED | VENDEVTSTRCVDEN | RESERVED_11 | RESERVED_10 | ERRTICERREVTEN | L1SUSPEN |
| R | R/W | NONE | R/W | R | R | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOFTEVTEN | U3L2L1SUSPEN | HIBERNATIONREQEVTEN | WKUPEVTEN | ULSTCNGEN | CONNECTDONEEVTEN | USBRSTEVTEN | DISSCONNEVTEN |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED_31_17 | R | 0h | Reserved |
| 16 | ECCERREN | R | 0h | ECC Error Enable. If this bit is set to 1, the controller reports an ECC error to the software when an uncorrectable ECC occurs internally. Reset Source: rst_mod_g_rst_n |
| 15 | RESERVED_15 | R | 0h | Reserved |
| 14 | L1WKUPEVTEN | R/W | 0h | L1 Resume Detected Event Enable. Note: If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled, then this bit is for L1 Resume Detected Event Enable. Reset Source: rst_mod_g_rst_n |
| 13 | RESERVED | NONE | 0h | Reserved |
| 12 | VENDEVTSTRCVDEN | R/W | 0h | Vendor Device Test LMP Received Event [VndrDevTstRcvedEn] Reset Source: rst_mod_g_rst_n |
| 11 | RESERVED_11 | R | 0h | Reserved |
| 10 | RESERVED_10 | R | 0h | Reserved |
| 9 | ERRTICERREVTEN | R/W | 0h | Erratic Error Event Enable Reset Source: rst_mod_g_rst_n |
| 8 | L1SUSPEN | R/W | 0h | L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled, this bit is for L1 Suspend Event Enable. Reset Source: rst_mod_g_rst_n |
| 7 | SOFTEVTEN | R/W | 0h | Start of [u]frame Reset Source: rst_mod_g_rst_n |
| 6 | U3L2L1SUSPEN | R/W | 0h | U3/L2 or U3/L2L1 Suspend Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled, then this bit is for U3/L2 Suspend Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled, then this bit is for U3/L2L1 Suspend Event Enable. Reset Source: rst_mod_g_rst_n |
| 5 | HIBERNATIONREQEVTEN | R/W | 0h | This bit enables/disables the generation of the Hibernation Request Event. Reset Source: rst_mod_g_rst_n |
| 4 | WKUPEVTEN | R/W | 0h | U3/L2 or U3/L2L1 Resume Detected Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled, then this bit is for U3/L2 Resume Detected Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled, then this bit is for U3/L2L1 Resume Detected Event Enable. Reset Source: rst_mod_g_rst_n |
| 3 | ULSTCNGEN | R/W | 0h | USB/Link State Change Event Enable Reset Source: rst_mod_g_rst_n |
| 2 | CONNECTDONEEVTEN | R/W | 0h | Connection Done Enable Reset Source: rst_mod_g_rst_n |
| 1 | USBRSTEVTEN | R/W | 0h | USB Reset Enable Reset Source: rst_mod_g_rst_n |
| 0 | DISSCONNEVTEN | R/W | 0h | Disconnect Detected Event Enable Reset Source: rst_mod_g_rst_n |