SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Voltage domain a VID actual code used as reference by Firmware to set the various voltage domain supply voltages. Reset defaults are sourced from efuse for each OPP. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary.
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| Instance Name | Physical Address |
|---|---|
| WKUP_VTM0 | 00B0 0104h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| OPP_3 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| OPP_2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OPP_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OPP_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | OPP_3 | R/W | 0h | OPP 3 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[j]_opp_3. Reset Source: mod_por_rst_n |
| 23:16 | OPP_2 | R/W | 0h | OPP 2 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[j]_opp_2. Reset Source: mod_por_rst_n |
| 15:8 | OPP_1 | R/W | 0h | OPP 1 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[j]_opp_1. Reset Source: mod_por_rst_n |
| 7:0 | OPP_0 | R/W | 0h | OPP 0 default VID. VID code that represents the required VD value in this Voltage domain to operate at. Valid values are from 0x1e to 0x91. Any value outside that range indicates not implemented including 0x0. This is SOC and device/chip specific. Reset value is from e-fuse at POR, efuse_vd[j]_opp_0. Reset Source: mod_por_rst_n |