SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
STP Trace Control Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 9800h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED3 | MOD_FIFOFULL | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DATA_FIFOFULL | RESERVED2 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED2 | COMPEN | RESERVED1 | SYNCEN | TSEN | RESERVED | ||
| R | R/W | R | R | R/W | R | ||
| 0h | 0h | 0h | 1h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED3 | R | 0h | Reserved, returns 0 |
| 24 | MOD_FIFOFULL | R | 0h | STPMI2ATB internal MID packet fifo is full |
| 23 | DATA_FIFOFULL | R | 0h | STPMI2ATB internal Data packet fifo is full |
| 22:6 | RESERVED2 | R | 0h | Reserved, returns 0 |
| 5 | COMPEN | R/W | 0h | Compression of Data enable |
| 4:3 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 2 | SYNCEN | R | 1h | The value 1 indicates STPASYNC is supported |
| 1 | TSEN | R/W | 0h | Timestamp Enable. This bit is static and should not be changed dynamically. This should be changed before client is enabled. |
| 0 | RESERVED | R | 0h | Reserved, returns 0 |