SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt status register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RFU5 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RFU5 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RFU5 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFU5 | RPCINTS | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RFU5 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 0 | RPCINTS | R | 0h | HyperBus Memory Interrupt.0 -No interrupt.1 - This bit displays interrupt from INT# signal of HyperBus memory. Reset Source: mod_g_rst_n |