SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Debug Control Register This register is used by debug software to control all of the basic debug functions.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0010h |
| C7X256V1_DEBUG | 0007 3800 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_3 | CANCEL_EXE | RESERVED_2 | RESET_REQ | RESERVED | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EXE_IGNORE_DBGM | EXE_IGNORE_HPI | EXT_HALT_EN | EXT_RUN_EN | EXT_DBG_EN | AETBP_EN | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 1h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SINGLE_STEP_TYPE | HWBP_EN | SWBP_EN | SINGLE_STEP_EN | EXMODE | HALT_LD | HALT | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_3 | R/W | 0h | reserved |
| 30 | CANCEL_EXE | R/W | 0h | Cancel Execution Control Request This bit is used to cancel an execution control request |
| 29:26 | RESERVED_2 | R/W | 0h | reserved |
| 25 | RESET_REQ | R/W | 0h | CPU Reset Request |
| 24:14 | RESERVED | R/W | 0h | reserved |
| 13 | EXE_IGNORE_DBGM | R/W | 0h | Ignore DBGM When Halting This bit is used to grant privileges to ignore the DBGM flag when servicing an execution control command that halts code execution |
| 12 | EXE_IGNORE_HPI | R/W | 0h | Ignore HPI This bit determines if execution requests issued via DBG_CNTL will honor or ignore HPI state |
| 11 | EXT_HALT_EN | R/W | 0h | Enable for External Debug Halt Trigger This bit enables the use of the external debug halt trigger [dbg_halt_req] to support halting the CPU |
| 10 | EXT_RUN_EN | R/W | 0h | Enable for External Debug Run Trigger This bit enables the use of the external debug run trigger [dbg_run_req] to support running the CPU |
| 9 | EXT_DBG_EN | R/W | 1h | Enable for External Debug Enable This bit enables allows the use of the external debug enable qualifier [dbg_enable] to support debug when coming out of a non-functional state |
| 8 | AETBP_EN | R/W | 0h | AET Generated Breakpoint Halt Enable This bit enables halting on the AET imprecise breakpoint debug event |
| 7 | SINGLE_STEP_TYPE | R/W | 0h | Single Step Type This bit defines the interrupt behavior while single-stepping |
| 6 | HWBP_EN | R/W | 0h | Hardware Breakpoint Halt Enable NOTE: Each hardware breakpoint resource also has a local enable |
| 5 | SWBP_EN | R/W | 0h | Software Breakpoint Halt Enable This bit enables halting on software breakpoint detection NOTE: If a SWBP opcode is fetched when this enable bit is not set then it is executed as a NOP |
| 4 | SINGLE_STEP_EN | R/W | 0h | Single Step Execution Enable This bit enables single step operation NOTE: See DBG_CNTL:SINGLE_STEP_TYPE for additional information |
| 3:2 | EXMODE | R/W | 0h | Execution Mode This bit controls the setting of the execution mode |
| 1 | HALT_LD | R/W | 0h | Global Debug Run Control Load This bit determines if a DBG_CNTL register write can update the HALT field This bit is simply an enable during writes, has no storage, and is always read as zero |
| 0 | HALT | R/W | 0h | Global Debug Run Control This bit controls the global execution state This bit will be read as being set upon entry to HALTED state due to the halted state being entered because of a debug event |