SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enhanced Control register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0090h |
| UART1 | 0281 0090h |
| UART2 | 0282 0090h |
| UART3 | 0283 0090h |
| UART4 | 0284 0090h |
| UART5 | 0285 0090h |
| UART6 | 0286 0090h |
| WKUP_UART0 | 2B30 0090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLEAR_TX_PE | TX_EN | RX_EN | TX_RST | RX_RST | A_MULTIDROP | |
| R | W | R/W | R/W | W | W | W | |
| 0h | 0h | 1h | 1h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | |
| 7:6 | RESERVED | R | 0h | |
| 5 | CLEAR_TX_PE | W | 0h | Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only] Reset Source: mod_g_arstn |
| 4 | TX_EN | R/W | 1h | Enables/Disables the transmitter 0 Transmitter is shut down 1 Transmitter is working |
| 3 | RX_EN | R/W | 1h | Enables/Disables the receiver 0 Receiver is shut down 1 Receiver is operating |
| 2 | TX_RST | W | 0h | Writing '1' resets the transmitter Reset Source: mod_g_arstn |
| 1 | RX_RST | W | 0h | Writing '1' resets the receiver Reset Source: mod_g_arstn |
| 0 | A_MULTIDROP | W | 0h | In multi-drop mode, when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set, signaling an address Reset Source: mod_g_arstn |