SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The L2 MISS Counter register holds the number of L2 Misses to the Remote data storage memory.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 007Ch |
| RL2_0 | 2500 107Ch |
| RL2_2 | 2500 207Ch |
| RL2_3 | 2500 307Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MISS | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MISS | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MISS | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MISS | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | MISS | R/W | 0h | The ~imiss Counts the number of misses to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over, it will stop counting at all ones. |