SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
AET PC Part 1 Read Register This register exposes bits 63-32 of the PC captured as a result of a trigger event specified in AET_PC_0:CAP_SRC.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 1018h |
| C7X256V1_DEBUG | 0007 3800 1018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CPC | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CPC | R | 0h | Captured PC[63:32] The PC is recorded when the trigger event specified by AET_PC:CAP_SRC occurs The recorded PC is the state of the PC that caused or was present when the conditions were suitable for the trigger event to be set This register is loaded continuously when the trigger event is in the inactive state |