SPRUJC6 User guide

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.7.4.1.2.71 OSPI_FLASH_CFG_DEV_DELAY_REG Register

1.2.71.1 OSPI_FLASH_CFG_DEV_DELAY_REG Register (Offset = Ch) [reset = 0h]

Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.

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Table 14-13563 Instance Table

Instance Name	Physical Address
FSS0	0FC4 000Ch

Figure 14-6707 OSPI_FLASH_CFG_DEV_DELAY_REG Name Register

31	30	29	28	27	26	25	24
D_NSS_FLD
R/W
0h
23	22	21	20	19	18	17	16
D_BTWN_FLD
R/W
0h
15	14	13	12	11	10	9	8
D_AFTER_FLD
R/W
0h
7	6	5	4	3	2	1	0
D_INIT_FLD
R/W
0h

Table 14-13564 OSPI_FLASH_CFG_DEV_DELAY_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	D_NSS_FLD	R/W	0h	Clock Delay for Chip Select Deassert: Delay in initiator reference clocks for the length that the initiator mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period.
23:16	D_BTWN_FLD	R/W	0h	Clock Delay for Chip Select Deactivation: Delay in initiator reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different targets and requires the transmit FIFO to be empty.
15:8	D_AFTER_FLD	R/W	0h	Clock Delay for Last Transaction Bit: Delay in initiator reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default, the chip select will be deasserted on the cycle following the completion of the current transaction.
7:0	D_INIT_FLD	R/W	0h	Clock Delay with n_ss_out: Delay in initiator reference clocks between setting n_ss_out low and first bit transfer.