SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Reading this register returns the upper 16 bits of the binary debug time and causes the lower 32 bits to be latched.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 6000 2024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | BINTIMEHI | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BINTIMEHI | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | R | 0h | Reserved, returns 0 |
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:0 | BINTIMEHI | R | 0h | Upper 16 bits of the timer |