SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Debug Capabilities Register This register is used by debug software to determine which debug modules are present and how many instances of each module exist.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0000h |
| C7X256V1_DEBUG | 0007 3800 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DBG_EM_SUP | DBG_RT_INT_SUP | DBG_WP_DATA_SUP | DBG_OWN_SUP | DBG_INDIRECT_SUP | DBG_SWBP_SUP | DBG_RESET_SUP | SYS_EXE_REQ |
| R | R | R | R | R | R | R | R |
| 1h | 1h | 0h | 1h | 1h | 1h | 1h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TRIG_OUTPUT | TRIG_INPUT | TRIG_CHNS | NUM_CNTRS | ||||
| R | R | R | R | ||||
| 1h | 1h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NUM_WPS | NUM_BPS | ||||||
| R | R | ||||||
| 1h | 4h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REV_MAJ | REV_MIN | ||||||
| R | R | ||||||
| 4h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DBG_EM_SUP | R | 1h | EM Mode Support |
| 30 | DBG_RT_INT_SUP | R | 1h | RT Mode Support |
| 29 | DBG_WP_DATA_SUP | R | 0h | WP Data Qualification Support |
| 28 | DBG_OWN_SUP | R | 1h | Ownership Support |
| 27 | DBG_INDIRECT_SUP | R | 1h | Indirect Debug Memory Port Support |
| 26 | DBG_SWBP_SUP | R | 1h | SWBP Support |
| 25 | DBG_RESET_SUP | R | 1h | CPU Reset Support |
| 24 | SYS_EXE_REQ | R | 0h | IDLE Status and Control |
| 23 | TRIG_OUTPUT | R | 1h | Trigger Output |
| 22 | TRIG_INPUT | R | 1h | Trigger Input |
| 21:20 | TRIG_CHNS | R | 0h | Number of Trigger Channels Supported |
| 19:16 | NUM_CNTRS | R | 0h | Number of Counters Implemented |
| 15:12 | NUM_WPS | R | 1h | Number of HWWP modules implemented |
| 11:8 | NUM_BPS | R | 4h | Number of HWBP modules implemented |
| 7:4 | REV_MAJ | R | 4h | The Major Revision number of this module |
| 3:0 | REV_MIN | R | 0h | The Minor Revision number of this module The first minor revision will be 0000b |