SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enet Port N Mac Status
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 3334h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| IDLE | E_IDLE | P_IDLE | MAC_TX_IDLE | TORF | TORF_PRI | ||
| R | R | R | R | R | R | ||
| 1h | 1h | 1h | 1h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TX_PFC_FLOW_ACT | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RX_PFC_FLOW_ACT | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXT_RX_FLOW_EN | EXT_TX_FLOW_EN | EXT_GIG | EXT_FULLDUPLEX | RESERVED | RX_FLOW_ACT | TX_FLOW_ACT |
| NONE | R | R | R | R | NONE | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | IDLE | R | 1h | Enet IDLE. The Ethernet port (express and prempt) are in the Idle state (valid after an Idle command) 0h The port is not in the Idle state. 1h The port is in the Idle state. |
| 30 | E_IDLE | R | 1h | Express MAC is Idle. |
| 29 | P_IDLE | R | 1h | Prempt MAC is Idle. |
| 28 | MAC_TX_IDLE | R | 1h | Mac Transmit Idle. Both Prempt and Express MAC Transmit are in Idle state. The transmit clock must be running for this to go idle. |
| 27 | TORF | R | 0h | Top of receive FIFO flow control trigger occurred. This bit is write one to clear. |
| 26:24 | TORF_PRI | R | 0h | The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. This field is write 7h to clear. |
| 23:16 | TX_PFC_FLOW_ACT | R | 0h | Transmit Priority Based Flow Control Active (priority 7 down to 0) |
| 15:8 | RX_PFC_FLOW_ACT | R | 0h | Receive Priority Based Flow Control Active (priority 7 down to 0) |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6 | EXT_RX_FLOW_EN | R | 0h | External Receive Flow Control Enable. This is the value of the CPSW_PN_MAC_CONTROL_REG_k[19] EXT_RX_FLOW_EN input bit. |
| 5 | EXT_TX_FLOW_EN | R | 0h | External Transmit Flow Control Enable. This is the value of the CPSW_PN_MAC_CONTROL_REG_k[20] EXT_TX_FLOW_EN input bit. |
| 4 | EXT_GIG | R | 0h | External GIG. This is the value of the [4] EXT_GIG input bit. |
| 3 | EXT_FULLDUPLEX | R | 0h | External Fullduplex. This is the value of the [3] EXT_FULLDUPLEX input bit. |
| 2 | RESERVED | NONE | 0h | Reserved |
| 1 | RX_FLOW_ACT | R | 0h | Receive Flow Control Active. When asserted, indicates that receive flow control is enabled and triggered. |
| 0 | TX_FLOW_ACT | R | 0h | Transmit Flow Control Active. When asserted, this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete. |