SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Timer IRQSTATUS RAW Register. This register indicates the raw status of the interrupt. It can be written by SW for testing. This register exists only if NUMTIMR > 0
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8C04h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TIM_INTN_IRQ | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TIM_INTN_IRQ | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TIM_INTN_IRQ | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIM_INTN_IRQ | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TIM_INTN_IRQ | R/W | 0h | IRQSTATUS_RAW value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT). |